View XCB56011BU95_408636.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by: DSP56011/D
DSP56011
Advance Information
24-BIT DVD DIGITAL SIGNAL PROCESSOR
The DSP56011 is a high-performance programmable Digital Signal Processor (DSP) developed for Digital Versatile Disc (DVD), High-Definition Television (HDTV), and Advanced Set-top audio decoding. The DSP56011 is optimized with audio-specific peripherals and customized memory configuration, and may be programmed with Motorola's certified software for Dolby AC-3 5.1 Channel Surround, Dolby Pro Logic, and MPEG1 Layer 2. These applications use Motorola's 24-bit DSP56000 architecture and are the highest quality solutions available. Flexible peripheral modules and interface software allow simple connection to a wide variety of video/ system decoders. In addition, the DSP56011 offers switchable memory space configuration, a large user-definable Program ROM and two independent data RAMs and ROMs, a Serial Audio Interface (SAI), Serial Host Interface (SHI), Parallel Host Interface (HI) with Direct Memory Access (DMA) for communicating with other processors, dedicated I/O lines, on-chip Phase Lock Loop (PLL), On-Chip Emulation (OnCETM) port, and on-chip Digital Audio Transmitter (DAX). Figure 1 shows the functional blocks of the DSP56011.
IN
9 5 2 Serial Audio Interface (SAI) Serial Host Interface (SHI) Digital Audio Transmitter (DAX) Address Generation Unit PAB XAB YAB GDB PDB XDB YDB Program Program Decode Address Controller Generator Program Control Unit 4
15 Parallel Host Interface (HI) Expansion Area 24-Bit DSP56000 Core
8 General Purpose I/O (GPIO)
PR
EL
Internal Data Bus Switch OnCETM Port Clock PLL Gen. Program Interrupt Controller 3 4 EXTAL
Rev. 1
IM
IRQA, IRQB, NMI, RESET
AR
Program Memory X Data Memory
Figure 1 DSP56011 Block Diagram
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Preliminary Information
(c) MOTOROLA, INC. 1996, 1997
Y
16-Bit Bus 24-Bit Bus Y Data Memory Data ALU 24 x 24 + 56 56-Bit MAC Two 56-Bit Accumulators
AA1271
DSP56011
TABLE OF CONTENTS
SECTION 1 SECTION 2 SECTION 3 SECTION 4 SECTION 5
SIGNAL/CONNECTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 1-1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
FOR TECHNICAL ASSISTANCE:
Telephone: Email: Internet:
1-800-521-6274
Data Sheet Conventions
This data sheet uses the following conventions:
PR
Examples:
Note:
EL
"asserted" "deasserted" Signal/Symbol PIN PIN PIN PIN
OVERBAR
IM
Logic State True False True False
Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) Means that a high true (active high) signal is high or that a low true (active low) signal is low Means that a high true (active high) signal is low or that a low true (active low) signal is high Signal State Asserted Deasserted Asserted Deasserted Voltage VIL/VOL VIH/VOH VIH/VOH VIL/VOL
Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
ii
DSP56011 Technical Data Sheet, Rev. 1
IN
dsphelp@dsp.sps.mot.com
http://www.motorola-dsp.com
Preliminary Information MOTOROLA
AR
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Y
DSP56011 Features
FEATURES
Digital Signal Processing Core
* Efficient, object-code compatible, 24-bit DSP56000 family DSP engine
- - - - - - - - - - -
Highly parallel instruction set with unique DSP addressing modes Two 56-bit accumulators including extension byte
Parallel 24 x 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles) Double precision 48 x 48-bit multiply with 96-bit result in 6 instruction cycles 56-bit addition/subtraction in 1 instruction cycle
Fractional and integer arithmetic with support for multi-precision arithmetic Hardware support for block-floating point Fast Fourier Transforms (FFT) Hardware nested DO loops
Zero-overhead fast interrupts (2 instruction cycles)
Four 24-bit internal data buses and three 16-bit internal address buses for simultaneous accesses to one program and two data memories
PR
Preliminary Information MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 iii
EL
IM
PLL-based clocking with a wide range of frequency multiplications (1 to 4096) and power saving clock divider (2i : i = 0 to 15), which reduces clock noise
IN
AR
Y
-
47.5 Million Instructions Per Second (MIPS) with 21.05 ns instruction cycle at 95 MHz
DSP56011 Features
Memory
* * * * * * Modified Harvard architecture allows simultaneous access to program and data memories 12800 x 24-bit on-chip Program ROM1 4096 x 24-bit on-chip X-data RAM and 3584 x 24-bit on-chip X-data ROM1 512 x 24-bit on-chip Program RAM and 64 x 24-bit bootstrap ROM 4352 x 24-bit on-chip Y-data RAM and 2048 x 24-bit on-chip Y-data ROM1
Table 1 lists the memory configurations of the DSP56011.
Table 1 DSP56011 Internal Memory Configurations
Memory Type Program RAM X data RAM Y data RAM Program ROM X data ROM Y data ROM
0.5 K 4.0 K 4.25 K
IN
1.25 K 3.25 K 4.25 K 12.5 K 3.5 K 2.0 K
No Switch (PEA = 0, PEB = 0)
Switch A (PEA = 1, PEB = 0)
IM
12.5 K 3.5 K 2.0 K
PR
iv
EL
1.These ROMs may be factory programmed with data/program provided by the application developer.
Preliminary Information DSP56011 Technical Data Sheet, Rev. 1 MOTOROLA
AR
Switch B (PEA = 0, PEB = 1) 2.0 K 3.25 K 3.5 K 12.5 K 3.5 K 2.0 K
As much as 2304 x 24 bits of X- and Y-data RAM can be switched to Program RAM, giving a total of 2816 x 24 bits of Program RAM
Y
Switch A+B (PEA = 1, PEB = 1) 2.75 K 2.5 K 3.5 K 12.5 K 3.5 K 2.0 K
DSP56011 Features
Peripheral and Support Circuits
* SAI includes: - - - - * Two receivers and three transmitters Master or slave capability I2S, Sony, and Matshushita audio protocol implementations Two sets of SAI interrupt vectors
SHI features: - - - - Single master capability SPI and I2C protocols 10-word receive FIFO
Support for 8-, 16- and 24-bit words.
* * * * * * * * *
DAX features one serial transmitter capable of supporting S/PDIF, IEC958, CP-340, and AES/EBU formats. Eight dedicated, independent, programmable GPIO lines
On-chip peripheral registers memory mapped in data memory space OnCE port for unobtrusive, processor speed-independent debugging Software programmable PLL-based frequency synthesizer for the core clock Power saving Wait and Stop modes
PR
Preliminary Information MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 v
EL
5 V power supply
Fully static, HCMOS design from specified operating frequency down to dc 100-pin plastic Thin Quad Flat Pack (TQFP) surface-mount package
IM
IN
*
Byte-wide Parallel Host Interface with DMA support capable of reconfiguration as fifteen General Purpose Input/Output (GPIO) lines
AR
Y
DSP56011 Documentation
DOCUMENTATION
Table 2 lists the documents that provide a complete description of the DSP56011 and are required to design properly with the part. Documentation is available from a local Motorola distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or through the Motorola DSP home page on the Internet (the source for the latest information).
Table 2 Additional DSP56011 Documentation
Document Name DSP56000 Family Manual DSP56011 User's Manual DSP56011 Technical Data Description
Detailed description of memory, peripherals, and interfaces Electrical and timing specifications, and pin and package descriptions
PR
Preliminary Information vi DSP56011 Technical Data Sheet, Rev. 1 MOTOROLA
EL
IM
IN
AR
Detailed description of the 56000-family architecture and the 24-bit core processor and instruction set
Y
Order Number DSP56KFAMUM/AD DSP56011UM/AD DSP56011/D
SECTION
1
SIGNAL/CONNECTION DESCRIPTIONS
SIGNAL GROUPINGS
Table 1-1 DSP56011 Functional Signal Groupings
Functional Group Power (VCC) Ground (GND) PLL Interrupt and Mode Control Host Interface (HI) Serial Host Interface (SHI)
IN
Port B
IM
Serial Audio Interface (SAI)
General Purpose Input/Output (GPIO) Digital Audio Transmitter (DAX) OnCE Port
EL PR
MOTOROLA
Figure 1-1 is a diagram of DSP56011 signals by functional group.
Preliminary Information DSP56011 Technical Data Sheet, Rev. 1 1-1
AR
Number of Signals 13 17 4 4 15 5 9 8 2 4
The input and output signals of the DSP56011 are organized into ten functional groups, as shown in Table 1-1 and as illustrated in Figure 1-1.
Y
Detailed Description Table 1-2 Table 1-3 Table 1-4 Table 1-5 Table 1-6 Table 1-7 Table 1-8 Table 1-9 Table 1-10 Table 1-11 Table 1-12
Signal/Connection Descriptions Signal Groupings
DSP56011
VCCP VCCQ VCCA VCCD VCCH VCCS Power Inputs: PLL Internal Logic A D HI SHI Host Interface (HI) Port 8 HI H0-H7 HOA0 HOA1 HOA2 HR/W HEN HOREQ HACK Port B GPIO PB0-PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14
4 2 1 3 2
Serial Host Interface (SHI)
PLOCK PCAP PINIT EXTAL
PLL
MODA/IRQA MODB/IRQB MODC/NMI RESET
IM
Interrupt/ Mode Control
EL
1-2
IN
Serial Audio Interface (SAI) Rec0 Rec1 Tran0 Tran1 Tran2 General Purpose Input/Output (GPIO) 8 GPIO0-GPIO7 Digital Audio Transmitter (DAX) ADO ACI Debug DSI DSCK DSO DR Non-Debug OS0 OS1 DSO DR OnCETM Port
PR
Figure 1-1 Signals Identified by Functional Group
Preliminary Information DSP56011 Technical Data Sheet, Rev. 1 MOTOROLA
AR
WSR SCKR SDI0 SDI1 WST SCKT SDO0 SDO1 SDO2
GNDP GNDQ GNDA GNDD GNDH GNDS
4 3 2 4 3
Grounds: PLL Internal Logic A D HI SHI
SPI Mode MOSI SS MISO SCK HREQ
Y
I2C Mode HA0 HA2 SDA SCL HREQ
Signal/Connection Descriptions Power
POWER
Table 1-2 Power Inputs
Power Name VCCP Description PLL Power--VCCP is VCC dedicated for Phase Lock Loop (PLL) use. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. VCCP should be bypassed to GNDP by a 0.1 F capacitor located as close as possible to the chip package.
VCCQ
VCCA
A Power--VCCA is an isolated power for sections of the internal chip logic. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. D Power--VCCD is an isolated power for sections of the internal chip logic. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. Host Power--VCCH is an isolated power for the HI I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors.
VCCD
VCCH
PR
Preliminary Information MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 1-3
EL
IM
VCCS
Serial Host Power--VCCS is an isolated power for the SHI I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors.
IN
AR
Quiet Power--VCCQ is an isolated power for the internal processing logic. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors.
Y
Signal/Connection Descriptions Ground
GROUND
Table 1-3 Grounds
Ground Name GNDP Description PLL Ground--GNDP is ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. VCCP should be bypassed to GNDP by a 0.1 F capacitor located as close as possible to the chip package.
GNDQ
GNDA
A Ground--GNDA is an isolated ground for sections of the internal logic. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. D Ground--GNDD is an isolated ground for sections of the internal logic. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. Host Ground--GNDH is an isolated ground for the HI I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors.
GNDD
GNDH
PR
Preliminary Information 1-4 DSP56011 Technical Data Sheet, Rev. 1 MOTOROLA
EL
IM
GNDS
Serial Host Ground--GNDS is an isolated ground for the SHI I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors.
IN
AR
Internal Logic Ground--GNDQ is an isolated ground for the internal processing logic. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors.
Y
Signal/Connection Descriptions Phase Lock Loop (PLL)
PHASE LOCK LOOP (PLL)
Table 1-4 Phase Lock Loop Signals
Signal Name PLOCK Type Output State During Reset Indeterminate Signal Description Phase Locked--PLOCK is an output signal that, when driven high, indicates that the PLL has achieved phase lock. After Reset, PLOCK is driven low until lock is achieved. Note:
PCAP
Input
Input
PINIT
Input
Input
EXTAL
PR
Preliminary Information MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 1-5
EL
IM
Input Input
IN
PLL Capacitor--PCAP is an input connecting an off-chip capacitor to the PLL filter. Connect one capacitor terminal to PCAP and the other terminal to VCCP. If the PLL is not used, PCAP may be tied to VCC, GND, or left floating.
PLL Initial--During assertion of RESET, the value of PINIT is written into the PLL Enable (PEN) bit of the PLL Control Register, determining whether the PLL is enabled or disabled. External Clock/Crystal Input--EXTAL interfaces the internal crystal oscillator input to an external crystal or an external clock.
AR
PLOCK is a reliable indicator of the PLL lock state only after the chip has exited the Reset state. During hardware reset, the PLOCK state is determined by PINIT and the current PLL lock condition.
Y
Signal/Connection Descriptions Interrupt and Mode Control
INTERRUPT AND MODE CONTROL
Table 1-5 Interrupt and Mode Control
Signal Name MODA Type Input State During Reset Signal Description
Input (MODA) Mode Select A--This input signal has three functions: * * * to work with the MODB and MODC signals to select the DSP's initial operating mode, to allow an external device to request a DSP interrupt after internal synchronization, and to turn on the internal clock generator when the DSP is in the Stop processing state, causing the DSP to resume processing.
IRQA
Input
EL
1-6
PR
IM
DSP56011 Technical Data Sheet, Rev. 1
IN
Preliminary Information
MODA is read and internally latched in the DSP when the processor exits the Reset state. The logic state present on the MODA, MODB, and MODC pins selects the initial DSP operating mode. Several clock cycles after leaving the Reset state, the MODA signal changes to the external interrupt request IRQA. The DSP operating mode can be changed by software after reset. External Interrupt Request A (IRQA)--The IRQA input is a synchronized external interrupt request. It may be programmed to be level-sensitive or negative-edge triggered. When the signal is edge-triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall time of the interrupt signal increases, the probability that noise on IRQA will generate multiple interrupts also increases.
While the DSP is in the Stop mode, asserting IRQA gates on the oscillator and, after a clock stabilization delay, enables clocks to the processor and peripherals. Hardware reset causes this input to function as MODA.
AR
Y
MOTOROLA
Signal/Connection Descriptions Interrupt and Mode Control
Table 1-5 Interrupt and Mode Control (Continued)
Signal Name MODB Type Input State During Reset Signal Description
Input (MODB) Mode Select B--This input signal has two functions: * * to work with the MODA and MODC signals to select the DSP's initial operating mode, and to allow an external device to request a DSP interrupt after internal synchronization.
IRQB
Input
PR
Preliminary Information MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 1-7
EL
IM
IN
External Interrupt Request B (IRQB)--The IRQB input is a synchronized external interrupt request. It may be programmed to be level-sensitive or negative-edge triggered. When the signal is edge-triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall time of the interrupt signal increases, the probability that noise on IRQB will generate multiple interrupts also increases. Hardware reset causes this input to function as MODB.
AR
MODB is read and internally latched in the DSP when the processor exits the Reset state. The logic state present on the MODA, MODB, and MODC pins selects the initial DSP operating mode. Several clock cycles after leaving the Reset state, the MODB signal changes to the external interrupt request IRQB. The DSP operating mode can be changed by software after reset.
Y
Signal/Connection Descriptions Interrupt and Mode Control
Table 1-5 Interrupt and Mode Control (Continued)
Signal Name MODC Type Input, edgetriggered State During Reset Signal Description
Input (MODC) Mode Select C--This input signal has two functions: * * to work with the MODA and MODB signals to select the DSP's initial operating mode, and to allow an external device to request a DSP interrupt after internal synchronization.
NMI
Input, edgetriggered
RESET
Input
PR
1-8
EL
IM
Active
DSP56011 Technical Data Sheet, Rev. 1
IN
Preliminary Information
Non-Maskable Interrupt Request--The NMI input is a negative-edge triggered external interrupt request. This is a level 3 interrupt that can not be masked out. Triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall time of the interrupt signal increases, the probability that noise on NMI will generate multiple interrupts also increases. Hardware reset causes this input to function as MODC. Reset--This input causes a direct hardware reset of the processor. When RESET is asserted, the DSP is initialized and placed in the Reset state. A Schmitt-trigger input is used for noise immunity. When the reset signal is deasserted, the initial DSP operating mode is latched from the MODA, MODB, and MODC signals. The DSP also samples the PINIT signal and writes its status into the PEN bit of the PLL Control Register. When the DSP comes out of the Reset state, deassertion occurs at a voltage level and is not directly related to the rise time of the RESET signal. However, the probability that noise on RESET will generate multiple resets increases with increasing rise time of the RESET signal. For proper hardware reset to occur, the clock must be active, since a number of clock ticks are required for proper propagation of the hardware Reset state.
AR
MODC is read and internally latched in the DSP when the processor exits the Reset state. The logic state present on the MODA, MODB, and MODC pins selects the initial DSP operating mode. Several clock cycles after leaving the Reset state, the MODC signal changes to the Non-Maskable Interrupt request, NMI. The DSP operating mode can be changed by software after reset.
Y
MOTOROLA
Signal/Connection Descriptions Host Interface (HI)
HOST INTERFACE (HI)
The HI provides a fast parallel data to 8-bit port, which may be connected directly to the host bus. The HI supports a variety of standard buses, and can be directly connected to a number of industry standard microcomputers, microprocessors, DSPs, and DMA hardware.
Signal Name H0-H7
Type Input/ Output
State During Reset Input
Signal Description
Host Data Bus (H0-H7)--This data bus transfers data between the host processor and the DSP56011. When configured as a Host Interface port, the H0-H7 signals are tri-stated as long as HEN is deasserted. The signals are inputs unless HR/W is high and HEN is asserted, in which case H0-H7 become outputs, allowing the host processor to read the DSP56011 data. H0-H7 become outputs when HACK is asserted during HOREQ assertion. Port B GPIO 0-7 (PB0-PB7)--These signals are General Purpose I/O signals (PB0-PB7) when the Host Interface is not selected. After reset, the default state for these signals is GPIO input. Host Address0-Host Address 2 (HOA0-HOA2)--These inputs provide the address selection for each Host Interface register. Port B GPIO 8-10 (PB8-PB10)--These signals are General Purpose I/O signals (PB8-PB10) when the Host Interface is not selected. After reset, the default state for these signals is GPIO input.
PB0-PB7
HOA0-HOA2
PR
MOTOROLA
EL
PB8-PB10 Input/ Output
IM
Input Input
DSP56011 Technical Data Sheet, Rev. 1
IN
Preliminary Information
AR
Y
1-9
Table 1-6 Host Interface
Signal/Connection Descriptions Host Interface (HI)
Table 1-6 Host Interface (Continued)
Signal Name HR/W Type Input State During Reset Input Signal Description Host Read/Write--This input selects the direction of data transfer for each host processor access. If HR/W is high and HEN is asserted, H0-H7 are outputs and DSP data is transferred to the host processor. If HR/W is low and HEN is asserted, H0-H7 are inputs and host data is transferred to the DSP. HR/W must be stable when HEN is asserted.
After reset, the default state for this signal is GPIO input. HEN Input Input Host Enable--This input enables a data transfer on the host data bus. When HEN is asserted and HR/W is high, H0-H7 become outputs and the host processor may read DSP56011 data. When HEN is asserted and HR/W is low, H0-H7 become inputs. Host data is latched inside the DSP on the rising edge of HEN. Normally, a chip select signal derived from host address decoding and an enable strobe are used to generate HEN.
PB12
EL
PB13 Input/ Output
HOREQ
PR
1-10
IM
Input/ Output Opendrain Output Input Note:
DSP56011 Technical Data Sheet, Rev. 1
IN
Preliminary Information
Port B GPIO 12 (PB12)--This signal is a General Purpose I/O signal (PB12) when the Host Interface is not being used. After reset, the default state for this signal is GPIO input. Host Request--This signal is used by the Host Interface to request service from the host processor, DMA controller, or a simple external controller. HOREQ should always be pulled high when it is not in use.
Port B GPIO 13 (PB13)--This signal is a General Purpose (not open-drain) I/O signal (PB13) when the Host Interface is not selected. After reset, the default state for this signal is GPIO input.
AR
PB11
Input/ Output
Port B GPIO 11 (PB11)--This signal is a General Purpose I/O signal (PB11) when the Host Interface is not being used.
Y
MOTOROLA
Signal/Connection Descriptions Host Interface (HI)
Table 1-6 Host Interface (Continued)
Signal Name HACK Type Input State During Reset Input Signal Description Host Acknowledge--This input has two functions. It provides a host acknowledge handshake signal for DMA transfers and it receives a host interrupt acknowledge compatible with MC68000 Family processors. Note: HACK should always be pulled high when it is not in use.
PB14
Input/ Output
Port B GPIO 14 (PB14)--This signal is a General Purpose I/O signal (PB14) when the Host Interface is not selected. After reset, the default state for this signal is GPIO input.
PR
Preliminary Information MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 1-11
EL
IM
IN
AR
Y
Signal/Connection Descriptions Serial Host Interface (SHI)
SERIAL HOST INTERFACE (SHI)
The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I2C mode. Table 1-7 Serial Host Interface (SHI) Signals
Signal Name SCK Signal Type Input or Output State during Reset Tri-stated Signal Description
SCL
Input or Output
PR
1-12
EL
IM
SPI Serial Clock--The SCK signal is an output when the SPI is configured as a master, and a Schmitt-trigger input when the SPI is configured as a slave. When the SPI is configured as a master, the SCK signal is derived from the internal SHI clock generator. When the SPI is configured as a slave, the SCK signal is an input, and the clock signal from the external master synchronizes the data transfer. The SCK signal is ignored by the SPI if it is defined as a slave and the Slave Select (SS) signal is not asserted. In both the master and slave SPI devices, data is shifted on one edge of the SCK signal and is sampled on the opposite edge where data is stable. Edge polarity is determined by the SPI transfer protocol. The maximum allowed internally generated bit clock frequency is fosc/4 for the SPI mode, where fosc is the clock on EXTAL. The maximum allowed externally generated bit clock frequency is fosc/3 for the SPI mode.
DSP56011 Technical Data Sheet, Rev. 1
IN
Preliminary Information
I2C Serial Clock--SCL carries the clock for I2C bus transactions in the I2C mode. SCL is a Schmitt-trigger input when configured as a slave, and an open-drain output when configured as a master. SCL should be connected to VCC through a pull-up resistor. The maximum allowed internally generated bit clock frequency is fosc/6 for the I2C mode where fosc is the clock on EXTAL. The maximum allowed externally generated bit clock frequency is fosc/5 for the I2C mode. An external pull-up resistor is not required.
AR
Y
MOTOROLA
Signal/Connection Descriptions Serial Host Interface (SHI)
Table 1-7 Serial Host Interface (SHI) Signals (Continued)
Signal Name MISO Signal Type Input or Output State during Reset Tri-stated Signal Description
SDA
Input or opendrain Output
MOSI
Input or Output
PR
MOTOROLA
EL
HA0 Input
IM
Tri-stated
I2C Data and Acknowledge--In I2C mode, SDA is a Schmitttrigger input when receiving and an open-drain output when transmitting. SDA should be connected to VCC through a pull-up resistor. SDA carries the data for I2C transactions. The data in SDA must be stable during the high period of SCL. The data in SDA is only allowed to change when SCL is low. When the bus is free, SDA is high. The SDA line is only allowed to change during the time SCL is high in the case of start and stop events. A high to low transition of the SDA line while SCL is high is an unique situation, which is defined as the start event. A low to high transition of SDA while SCL is high is an unique situation, which is defined as the stop event. SPI Master-Out-Slave-In--When the SPI is configured as a master, MOSI is the master data output line. The MOSI signal is used in conjunction with the MISO signal for transmitting and receiving serial data. MOSI is the slave data input line when the SPI is configured as a slave. This signal is a Schmitttrigger input when configured for the SPI Slave mode. I2C Slave Address 0--This signal uses a Schmitt-trigger input when configured for the I2C mode. When configured for I2C Slave mode, the HA0 signal is used to form the slave device address. HA0 is ignored when it is configured for the I2C Master mode.
DSP56011 Technical Data Sheet, Rev. 1
IN
Preliminary Information
An external pull-up resistor is not required.
AR
SPI Master-In-Slave-Out--When the SPI is configured as a master, MISO is the master data input line. The MISO signal is used in conjunction with the MOSI signal for transmitting and receiving serial data. This signal is a Schmitt-trigger input when configured for the SPI Master mode, an output when configured for the SPI Slave mode, and tri-stated if configured for the SPI Slave mode when SS is deasserted. An external pull-up resistor is not required for SPI operation.
Y
1-13
Signal/Connection Descriptions Serial Host Interface (SHI)
Table 1-7 Serial Host Interface (SHI) Signals (Continued)
Signal Name SS Signal Type Input State during Reset Tri-stated Signal Description
HA2
Input
PR
1-14
EL
IM
HREQ
Input or Output
Tri-stated
DSP56011 Technical Data Sheet, Rev. 1
IN
Preliminary Information
I2C Slave Address 2--This signal uses a Schmitt-trigger input when configured for the I2C mode. When configured for the I2C Slave mode, the HA2 signal is used to form the slave device address. HA2 is ignored in the I2C Master mode. If SS is deasserted, the SHI ignores SCK clocks and keeps the MISO output signal in the high-impedance state. This signal is tri-stated during hardware, software, or individual reset (thus, there is no need for an external pull-up in this state).
Host Request--This signal is an active low Schmitt-trigger input when configured for the Master mode, but an active low output when configured for the Slave mode.
When configured for the Slave mode, HREQ is asserted to indicate that the SHI is ready for the next data word transfer and deasserted at the first clock pulse of the new data word transfer. When configured for the Master mode, HREQ is an input and when asserted by the external slave device, it will trigger the start of the data word transfer by the master. After finishing the data word transfer, the master will await the next assertion of HREQ to proceed to the next transfer. This signal is tri-stated during hardware, software, personal reset, or when the HREQ1-HREQ0 bits in the HCSR are cleared (no need for external pull-up in this state).
AR
SPI Slave Select--This signal is an active low Schmitt-trigger input when configured for the SPI mode. When configured for the SPI Slave mode, this signal is used to enable the SPI slave for transfer. When configured for the SPI Master mode, this signal should be kept deasserted (pulled high). If it is asserted while configured as SPI master, a bus error condition is flagged.
Y
MOTOROLA
Signal/Connection Descriptions Serial Audio Interface (SAI)
SERIAL AUDIO INTERFACE (SAI)
The SAI is composed of separate receiver and transmitter sections.
SAI Receive Section
The receive section of the SAI has four dedicated signals.
Signal Name SDI0
Signal Type Input
State during Reset Tristated
Serial Data Input 0--This is the receiver 0 serial data input.
SDI1
Input
Tristated
SCKR
Input or Output
PR
MOTOROLA
EL
WSR Input or Output Tristated
IM
Tristated
DSP56011 Technical Data Sheet, Rev. 1
IN
Preliminary Information
This signal is high impedance during hardware or software reset, while receiver 0 is disabled (R0EN = 0), or while the chip is in the Stop state. No external pull-up resistor is required. Serial Data Input 1--This is the receiver 1 serial data input. This signal is high impedance during hardware or software reset, while receiver 1 is disabled (R1EN = 0), or while the chip is in the Stop state. No external pull-up resistor is required. Receive Serial Clock--SCKR is an output if the receiver section is programmed as a master, and a Schmitt-trigger input if programmed as a slave. SCKR is high impedance if all receivers are disabled (personal reset) and during hardware or software reset, or while the chip is in the Stop state. No external pull-up is necessary. Receive Word Select--WSR is an output if the receiver section is programmed as a master, and a Schmitt-trigger input if programmed as a slave. WSR is used to synchronize the data word and to select the left/right portion of the data sample. WSR is high impedance if all receivers are disabled (personal reset), during hardware reset, during software reset, or while the chip is in the stop state. No external pull-up is necessary.
AR
Signal Description
Table 1-8 Serial Audio Interface (SAI) Receive Signals
Y
1-15
Signal/Connection Descriptions Serial Audio Interface (SAI)
SAI Transmit Section
The transmit section of the SAI has five dedicated signals. Table 1-9 Serial Audio Interface (SAI) Transmit Signals
Signal Name SDO0 Signal Type Output State during Reset Driven high Signal Description
SDO1
Output
Driven high
SDO2
Output
Driven high
PR
WST Input or Output
1-16
EL
Tristated
IM
SCKT
Input or Output
Tristated
DSP56011 Technical Data Sheet, Rev. 1
IN
Preliminary Information
Serial Data Output 1--SDO1 is the transmitter 1 serial output. SDO1 is driven high if transmitter 1 is disabled, during personal reset, hardware reset and software reset, or when the chip is in the Stop state. Serial Data Output 2--SDO2 is the transmitter 2 serial output. SDO2 is driven high if transmitter 2 is disabled, during personal reset, hardware reset and software reset, or when the chip is in the Stop state.
Transmit Serial Clock--This signal provides the clock for the Serial Audio Interface (SAI). The SCKT signal can be an output if the transmit section is programmed as a master, or a Schmitttrigger input if the transmit section is programmed as a slave. When the SCKT is an output, it provides an internally generated SAI transmit clock to external circuitry. When the SCKT is an input, it allows external circuitry to clock data out of the SAI. SCKT is tri-stated if all transmitters are disabled (personal reset), during hardware reset, software reset, or while the chip is in the Stop state. No external pull-up is necessary. Transmit Word Select--WST is an output if the transmit section is programmed as a master, and a Schmitt-trigger input if programmed as a slave. WST is used to synchronize the data word and select the left/right portion of the data sample. WST is tri-stated if all transmitters are disabled (personal reset), during hardware or software reset, or while the chip is in the Stop state. No external pull-up is necessary.
AR
Serial Data Output 0--SDO0 is the transmitter 0 serial output. SDO0 is driven high if transmitter 0 is disabled, during personal reset, hardware reset and software reset, or when the chip is in the Stop state.
Y
MOTOROLA
Signal/Connection Descriptions General Purpose Input/Output (GPIO)
GENERAL PURPOSE INPUT/OUTPUT (GPIO)
Table 1-10 General Purpose I/O (GPIO) Signals
Signal Name GPIO0- GPIO7 Signal Type Input or Output (standard or open-drain) State during Reset Disconnected internally Signal Description General Purpose Input/Output--These signals are used for control and handshake functions between the DSP and external circuitry. Each GPIO signal may be individually programmed to be one of four states: * Not connected * Input * Standard output * Open-drain output
DIGITAL AUDIO INTERFACE (DAX)
Table 1-11 Digital Audio Interface (DAX) Signals
ADO
EL
ACI Input
PR
MOTOROLA
IM
Output Tri-stated
Signal Name
Type
DSP56011 Technical Data Sheet, Rev. 1
IN
State During Reset
Output, driven Digital Audio Data Output--This signal is an high audio and non-audio output in the form of AES/ EBU, CP340 and IEC958 data in a biphase mark format. The signal is driven high when the DAX is disabled, and during hardware or software reset. Audio Clock Input--This is the DAX clock input. When programmed to use an external clock, this input supplies the DAX clock. The external clock frequency must 256, 384, or 512 times the audio sampling frequency (256 x Fs, 384 x Fs or 512 x Fs, respectively). The ACI signal is high impedance (tri-stated) only during hardware or software reset. If the DAX is not used, connect the ACI signal to ground through an external pull-down resistor to ensure a stable logic level at the input.
Preliminary Information 1-17
AR
Signal Description
Y
Signal/Connection Descriptions OnCE Port
OnCE PORT
Table 1-12 On-Chip Emulation Port (OnCE) Signals
Signal Name DSI Signal Type Input State during Reset Low Output Signal Description
OS0
Output
Chip Status 0--When the chip is not in Debug mode, this signal is an output that works with the OS1 signal to provide information about the chip status.
DSCK
Input
Low Output
EL
OS1 Output
PR
1-18
IM
Note:
DSP56011 Technical Data Sheet, Rev. 1
IN
Note:
If the OnCE interface is in use, an external pull-down resistor should be attached to this pin. If the OnCE interface is not in use, the resistor is not required.
Debug Serial Clock--The DSCK signal is used in Debug mode and supplies the serial input clock to the OnCE module to shift data into and out of the OnCE serial port. (Data is clocked into the OnCE port on the falling edge and is clocked out of the OnCE serial port on the rising edge.) The debug serial clock frequency must be no greater than 1/8 of the processor clock frequency. When switching from input to output, the signal is tri-stated. Chip Status 1--When the chip is not in Debug mode, this signal is an output that works with the OS0 signal to provide information about the chip status.
If the OnCE interface is in use, an external pull-down resistor should be attached to this pin. If the OnCE interface is not in use, the resistor is not required.
Preliminary Information MOTOROLA
AR
Debug Serial Input--In Debug mode, serial data or commands are provided as inputs to the OnCE controller via the DSI signal. Data is latched on the falling edge of the DSCK serial clock. Data is always shifted into the OnCE serial port Most Significant Bit (MSB) first. When switching from output to input, the signal is tri-stated.
Y
Signal/Connection Descriptions OnCE Port
Table 1-12 On-Chip Emulation Port (OnCE) Signals (Continued)
Signal Name DSO Signal Type Output State during Reset Pulled high Signal Description
EL PR
MOTOROLA
IM
Note: Note:
DR
Input
Input
DSP56011 Technical Data Sheet, Rev. 1
IN
Preliminary Information
The DSO signal also provides acknowledge pulses to the external command controller. When the chip enters the Debug mode, the DSO signal will be pulsed low to indicate (acknowledge) that the OnCE is waiting for commands. After the OnCE receives a read command, the DSO signal is pulsed low to indicate that the requested data is available and the OnCE serial port is ready to receive clocks in order to deliver the data. After the OnCE receives a write command, the DSO signal is pulsed low to indicate that the OnCE serial port is ready to receive the data to be written; after the data is written, another acknowledge pulse is provided.
Debug Request--A Debug Request (DR) input from an external command controller allows the user to enter the Debug mode of operation. When DR is asserted, it causes the DSP to finish the current instruction being executed, save the instruction pipeline information, enter the Debug mode, and wait for commands to be entered from the DSI line. While in Debug mode, the DR signal lets the user reset the OnCE controller by asserting it and deasserting it after receiving an acknowledge signal.
It may be necessary to reset the OnCE controller in cases where synchronization between the OnCE controller and external circuitry is lost.
DR must be deasserted after the OnCE responds with an acknowledge on the DSO signal and before sending the first OnCE command. Asserting DR causes the chip to exit the Stop or Wait state. Having DR asserted during the deassertion of RESET causes the DSP to enter Debug mode.
If the OnCE interface is not in use, attach an external pull-up resistor to the DR input.
AR
Y
1-19
Debug Serial Output--Data contained in one of the OnCE controller registers is provided through the DSO output signal, as specified by the last command received from the external command controller. Data is always shifted out the OnCE serial port MSB first. Data is clocked out of the OnCE serial port on the rising edge of DSCK.
Signal/Connection Descriptions OnCE Port
PR
Preliminary Information 1-20 DSP56011 Technical Data Sheet, Rev. 1 MOTOROLA
EL
IM
IN
AR
Y
SECTION
2
SPECIFICATIONS
INTRODUCTION
MAXIMUM RATINGS
PR
MOTOROLA
EL
Note: In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a "maximum" value for a specification will never occur in the same device that has a "minimum" value for another specification; adding a maximum to a minimum represents a condition that can never exist.
IM
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC).
DSP56011 Technical Data Sheet, Rev. 1
IN
CAUTION
Preliminary Information 2-1
AR
The DSP56011 is fabricated in high density CMOS with Transistor-Transistor Logic (TTL) compatible inputs and outputs. The DSP56011 specifications are preliminary and are from design simulations, and may not be fully tested or guaranteed at this early stage of the product life cycle. For design convenience, timings for 81 MHz and 95 MHz operation are included. Finalized specifications will be published after full characterization and device qualifications are complete.
Y
Specifications Thermal characteristics
Table 2-1 Maximum Ratings
Rating1 Supply Voltage All input voltages Current drain per pin excluding VCC and GND Operating temperature range Storage temperature
Notes: 1. 2.
Symbol VCC VIN I TJ TSTG
Value1, 2
Unit V V mA
-0.3 to +7.0 GND - 0.5 to VCC + 0.5
10 -40 to +105
THERMAL CHARACTERISTICS
Table 2-2 Thermal Characteristics
Characteristic Symbol
IN
RJA or JA RJC or JC JT
AR
TQFP Value 47 5.8 1.6
GND = 0 V, VCC = 5.0 V 5%, TJ = -40C to +105C, CL = 50 pF + 2 TTL Loads Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device.
Junction-to-ambient thermal resistance1 Junction-to-case thermal resistance2
IM
Thermal characterization parameter
Notes: 1.
PR
2-2
EL
2.
Junction-to-ambient thermal resistance is based on measurements on a horizontal-single-sided printed circuit board per SEMI G38-87 in natural convection.(SEMI is Semiconductor Equipment and Materials International, 805 East Middlefield Rd., Mountain View, CA 94043, (415) 964-5111) Measurements were done with parts mounted on thermal test boards conforming to specification EIA/JESD51-3. Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G3088, with the exception that the cold plate temperature is used for the case temperature.
Preliminary Information DSP56011 Technical Data Sheet, Rev. 1 MOTOROLA
Y
Unit
-55 to +125
C C
C/W C/W C/W
Specifications DC Electrical Characteristics
DC ELECTRICAL CHARACTERISTICS
Table 2-3 DC Electrical Characteristics
Characteristics Supply voltage Input high voltage * EXTAL * RESET * MODA, MODB, MODC * ACI, SHI inputs1 * All other inputs Input low voltage * EXTAL * MODA, MODB, MODC * ACI, SHI inputs1 * All other inputs Input leakage current * EXTAL, RESET, MODA, MODB, MODC, DR * Other Input Pins (@ 2.4 V/0.4 V) High impedance (off-state) input current (@ 2.4 V / 0.4 V) Output high voltage (IOH = -0.4 mA) Output low voltage (IOL = 3.2 mA) SCK/SCL IOL = 6.7 mA MISO/SDA IOL = 6.7 mA HOREQ IOL = 6.7 mA Symbol VCC VIHC VIHR VIHM VIHS VIH VILC VILM VILS VIL IIN Min 4.75 4.0 2.5 3.5 0.7 x VCC 2.0 -0.5 -0.5 -0.5 -0.5 -1 Typ 5.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 5.25 VCC VCC VCC VCC VCC Unit V V V V V V
AR
1 10 10 -- 0.4 -10 -10 2.4 -- -- -- -- -- -- 155 22 TBD 1.2 10 -- TBD TBD 2.0 --
IN
ITSI VOH VOL ICCI ICCW ICCS CIN
IM
EL
Internal Supply Current @ 95 MHz * Normal mode4 * Wait mode * Stop mode2 PLL supply current @ 95 MHz Input capacitance3
1. 2. 3. 4.
PR
Notes:
The SHI inputs are: MOSI/HA0, SS/HA2, MISO/SDA, SCK/SCL, and HREQ. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). PLL signals are disabled during Stop state. Periodically sampled and not 100% tested Maximum values can be derived using the methodology described in Section 4. Actual maximums are application dependent and may vary widely.
Preliminary Information MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 2-3
Y
0.6 2.0 0.3 x VCC 0.8 V V V V A A A V V mA mA mA mA pF
Specifications AC Electrical Characteristics
AC ELECTRICAL CHARACTERISTICS
The timing waveforms in the AC Electrical Characteristics are tested with a VIL maximum of 0.5 V and a VIH minimum of 2.4 V for all inputs, except EXTAL, RESET, MODA, MODB, MODC, ACI, and SHI inputs (MOSI/HA0, SS/HA2, MISO/SDA, SCK/SCL, HREQ). These inputs are tested using the input levels set forth in the DC Electrical Characteristics. AC timing specifications that are referenced to a device input signal are measured in production with respect to the 50% point of the respective input signal's transition. DSP56011 output levels are measured with the production test machine VOL and VOH reference levels set at 0.8 V and 2.0 V, respectively. All output delays are given for a 50 pF load unless otherwise specified. For load capacitance greater than 50 pF, the drive capability of the output pins typically decreases linearly: 1. At 1.5 ns per 10 pF of additional capacitance at all output pins except MOSI/HA0, MISO/SDA, SCK/SCL, HREQ 2. At 1.0 ns per 10 pF of additional capacitance at output pins MOSI/HA0, MISO/SDA, SCK/SCL, HREQ (in SPI mode only)
INTERNAL CLOCKS
IM
Symbol F TH TL TC ICYC
Characteristics
IN
Table 2-4 Internal Clocks
Minimum 0 ETHminimum 0.48 x TC 0.467 x TC ETLminimum 0.48 x TC 0.467 x TC
EL
Internal operation frequency Internal clock high period * with PLL disabled1 * with PLL enabled and MF 4 * with PLL enabled and MF > 4 Internal clock low period * with PLL disabled (see Note) * with PLL enabled and MF 4 * with PLL enabled and MF > 4 Internal clock cycle time Instruction cycle time
Note:
PR
2-4
See Table 2-5 on page 2-5 for External Clock (ET) specifications.
Preliminary Information DSP56011 Technical Data Sheet, Rev. 1 MOTOROLA
AR
Expression 95 MHz (DF x ETC)/MF 2 x TC
Y
Maximum ETHmaximum 0.52 x TC 0.533 x TC ETLmaximum 0.52 x TC 0.533 x TC
Specifications External Clock Operation
EXTERNAL CLOCK OPERATION
The DSP56011 system clock is externally supplied via the EXTAL pin. Timings shown in this document are valid for clock rise and fall times of 3 ns maximum. The 81 MHz speed allows the DSP56011 to take advantage of the 27 MHz system clock in DVD applications. Table 2-5 External Clock (EXTAL)
81 MHz No. Characteristics Frequency of external clock EXTAL 1 External clock input high--EXTAL * With PLL disabled (46.7%-53.3% duty cycle) * With PLL enabled (42.5%-57.5% duty cycle) External clock input low--EXTAL * With PLL disabled (46.7%-53.3% duty cycle) * With PLL enabled (42.5%-57.5% duty cycle) External clock cycle time * With PLL disabled * With PLL enabled Sym. Min 0 EF
AR
81 0 95 ETH 5.8 5.2 4.9 4.5 235500 235500 ETL 5.8 5.2 4.9 4.5 10.5 10.5 21.0 21.0 235500 409600 819200 235500 409600 819200 ETC 12.3 12.3 24.7 24.7 ICYC 2 ETL 4
2
IN
3 ETC
3
IM
1 ETH
4
PR
EL
Note:
Instruction cycle time = ICYC = 2 x TC * With PLL disabled * With PLL enabled
EXTAL input high and input low are measured at 50% of the input transition.
EXTAL
Figure 2-1 External Clock Timing
Preliminary Information MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 2-5
Y
95 MHz Unit Max Min Max MHz ns ns ns ns ns ns ns ns
AA0250
Specifications Phase Lock Loop (PLL) Characteristics
PHASE LOCK LOOP (PLL) CHARACTERISTICS
Table 2-6 Phase Lock Loop (PLL) Characteristics
Characteristics VCO frequency when PLL enabled PLL external capacitor (PCAP pin to VCCP)
Note:
Expression MF x EF MF x CPCAP @ MF 4 @ MF > 4
Min 10 MF x 340 MF x 380
Max f MF x 480 MF x 970
Unit MHz pF pF
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing
All Frequencies Unit Max No. Characteristics
10
Minimum RESET assertion width: * PLL disabled * PLL enabled1 Mode select setup time Mode select hold time
IM
IN
21 0 13 13
RESET, STOP, MODE SELECT, AND INTERRUPT TIMING
AR
Min 25 x TC 2500 x ETC -- -- -- -- -- -- 12 x TC + TH 11 x TC + TH -- --
Cpcap is the value of the PLL capacitor (connected between PCAP pin and VCCP) for MF = 1. The recommended value for Cpcap is 400 pF for MF 4 and 540 pF for MF > 4. The maximum VCO frequency is limited to the internal operation frequency, defined in Table 2-4.
14 15 16
EL
16a 18
Minimum edge-triggered interrupt request assertion width
PR
Minimum edge-triggered interrupt request deassertation width
Delay from IRQA, IRQB, NMI assertion to GPIO valid caused by first interrupt instruction execution * GPIO0-GPIO7 * PB0-PB14
Preliminary Information 2-6 DSP56011 Technical Data Sheet, Rev. 1 MOTOROLA
Y
ns ns ns ns ns ns ns ns
Specifications RESET, Stop, Mode Select, and Interrupt Timing
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (Continued)
All Frequencies No. Characteristics Min 22 Delay from General Purpose Output valid to interrupt request deassertion for level sensitive fast interrupts-- if second interrupt instruction is:2 * Single cycle * Two cycles Duration of IRQA assertion for recovery from stop state Max Unit
25 27
AR
12 -- 6 x TC+ TL 12 -- --
Notes:
1.
2.
EL
RESET
IM
10
This timing requirement is sensitive to the quality of the external PLL capacitor connected to the PCAP pin. For capacitor values less than or equal to 2 nF, asserting RESET according to this timing requirement will ensure proper processor initialization for capacitors with a delta C/C less than 0.5%. (This is typical for ceramic capacitors.) For capacitor values greater than 2 nF, asserting RESET according to this timing requirement will ensure proper processor initialization for capacitors with a delta C/C less than 0.01%. (This is typical for Teflon, polystyrene, and polypropylene capacitors.) However, capacitors with values greater than 2 nF with a delta C/C greater than 0.01% may require longer RESET assertion to ensure proper initialization. When using fast interrupts and IRQA and IRQB are defined as level-sensitive, timing 22 applies to prevent multiple interrupt service. To avoid these timing restrictions, negative-edge-triggered configuration is recommended when using fast interrupts. Long interrupts are recommended when using level-sensitive configuration.
IN
Figure 2-2 Reset Timing
Duration for level-sensitive IRQA assertion to ensure interrupt service (when exiting Stop mode) * Stable external clock, OMR Bit 6 = 1 * Stable external clock, PCTL Bit 17 = 1
PR
Preliminary Information MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 2-7
Y
TL - 31 (2 x TC) + TL - 31 ns ns ns ns ns VIHR
AA0251
Specifications RESET, Stop, Mode Select, and Interrupt Timing
RESET 14 VIHM MODA, MODB MODC VILM VIL 15
VIHR
VIH IRQA, IRQB, NMI
Figure 2-3 Operating Mode Select Timing
IRQA, IRQB, NMI IRQA, IRQB, NMI
16
IN
22 General Purpose I/O 27
16A
AR
AA0253 AA0254 AA0255 AA0256
Figure 2-4 External Interrupt Timing (Negative-Edge Triggered)
General Purpose I/O (Output) IRQA IRQB NMI
PR
2-8
EL
25 IRQA IRQA
Figure 2-7 Recovery from Stop State Using IRQA Interrupt Service
IM
18
Figure 2-5 External Level-Sensitive Fast Interrupt Timing
Figure 2-6 Recovery from Stop State Using IRQA
Preliminary Information DSP56011 Technical Data Sheet, Rev. 1 MOTOROLA
Y
AA0252
Specifications Host Interface (HI) Timing
HOST INTERFACE (HI) TIMING
Note: Active low lines should be "pulled up" in a manner consistent with the AC and DC specifications. Table 2-8 Host I/O Timing (All Frequencies)
Num 31 Characteristics HEN/HACK assertion width1 * CVR, ICR, ISR, RXL read * IVR, RXH/M read * Write Min TC + 31 26 13 Max -- -- -- Unit ns
32
HEN/HACK deassertion width1 * After TXL writes2 * After RXL reads3 * Between two CVR, ICR, or ISR reads
AR
13 2 x TC + 31 2 x TC + 31 2 x TC + 31 4 -- -- -- -- -- 3 -- -- 26 18 -- -- -- -- -- -- -- 45 -- -- -- 0 -- -- 2.5 0 3 0 3 0 3 3 TL + TC + TH TL + TC 0
34 35 36 37 38 39
Host data input hold time after HEN/HACK deassertion
IN
deassertion4
33
Host data input setup time before HEN/HACK deassertion
HEN/HACK assertion to output data valid
IM
HEN/HACK assertion to output data active from high impedance
HEN/HACK deassertion to output data high impedance5 Output data hold time after HEN/HACK Deassertion6
EL
40 41
HR/W low setup time before HEN assertion HR/W low hold time after HEN deassertion
HR/W high setup time to HEN assertion HR/W high hold time after HEN/HACK deassertion
PR
42
43
HOA0-HOA2 setup time before HEN assertion HOA0-HOA2 Hold Time After HEN Deassertion DMA HACK assertion to HOREQ
44
45 46
DMA HACK deassertion to HOREQ assertion4,5 * For DMA RXL read * For DMA TXL write * All other cases
Preliminary Information MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 2-9
Y
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Specifications Host Interface (HI) Timing
Table 2-8 Host I/O Timing (All Frequencies) (Continued)
Num 47 48 49
Notes:
Characteristics Delay from HEN deassertion to HOREQ assertion for RXL read4,5 Delay from HEN deassertion to HOREQ assertion for TXL write4,5 Delay from HEN assertion to HOREQ deassertion for RXL read, TXL write4,5
1. 2. 3. 4. 5. 6.
Min TL + TC + TH TL + TC
Max -- --
Unit ns ns
HOREQ (Output)
IM
41 36 35
HACK (Input)
HR/W (Input)
EL
H0-H7 (Output)
IN
31 32 42 37 38 Data Valid
AA1275
Figure 2-8 Host Interrupt Vector Register (IVR) Read
PR
Preliminary Information 2-10 DSP56011 Technical Data Sheet, Rev. 1 MOTOROLA
AR
See Host Port Considerations in Section 4 Design Considerations. This timing is applicable only if a write to the TXL is followed by writing the TXL, TXM, or TXH registers without first polling the TXDE or HOREQ flags, or waiting for HOREQ to be asserted. This timing is applicable only if a read from the RXL is followed by reading the RXL, RXM or RXH registers without first polling the RXDF or HOREQ flags, or waiting for HOREQ to be asserted. HOREQ is pulled up by a 1 k resistor. Specifications are periodically sampled and not 100% tested. May decrease to 0 ns for future versions
Y
3 58 ns
Specifications Host Interface (HI) Timing
HOREQ (Output) 49 HEN (Input) 43 HA2-HA0 (Input) Address Valid 41 HR/W (Input) 36 35 H0-H7 (Output) Data Valid 38 42 RXH Read 31 32 44 Address Valid RXM Read 47 RXL Read
37
IN
49 TXM Write 32 44 Address Valid 40 34 Data Valid Data Valid
AR
Data Valid Data Valid
AA1276
Figure 2-9 Host Read Cycle (Non-DMA Mode)
IM
TXH Write 31 Address Valid 39 33
HOREQ (Output)
HEN (Input) 43
EL
HA2-HA0 (Input)
PR
H0-H7 (Output)
HR/W (Input)
Figure 2-10 Host Write Cycle (Non-DMA Mode)
Preliminary Information MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 2-11
Y
Address Valid 48 TXL Write Address Valid Data Valid
AA1277
Specifications Host Interface (HI) Timing
HOREQ (Output) 45 31 HACK (Input) 36 35 H0-H7 (Output) Data Valid 38 Data Valid RXH Read 37 46 46 32 RXM Read RXL Read 46
AR
Data Valid 46 46 TXL Write TXM Write Data Valid Data Valid
Figure 2-11 Host DMA Read Cycle
HOREQ (Output) 45 31 HACK (Input) TXH Write
H0-H7 (Output)
IM
33 34 Data Valid
IN
46 32
PR
2-12
EL
Figure 2-12 Host DMA Write Cycle
Preliminary Information DSP56011 Technical Data Sheet, Rev. 1 MOTOROLA
Y
AA1278 AA1279
Specifications Serial Audio Interface (SAI) Timing)
SERIAL AUDIO INTERFACE (SAI) TIMING)
Table 2-9 Serial Audio Interface (SAI) Timing
81 MHz No. Characteristics Mode Master Slave Master Slave 113 Serial Clock low period Master Slave 114 Serial Clock rise/fall time Master Slave Expression Min 111 Minimum Serial Clock cycle = TSAICC (min) 112 Serial Clock high period 4 x TC 3 x TC + 5 0.5 x TSAICC - 8 0.35 x TSAICC 0.35 x TSAICC 8 49.4 42 Max -- Min 42 Max -- ns 95 MHz Unit
AR
14.7 -- 12.8 13 0.5 x TSAICC - 8 16.7 -- 14.7 -- -- 8 12.8 -- 0.15 x TSAICC 26 4 -- 6.3 -- -- -- -- 20 -- -- 13 40 40.2 19 -- -- -- 26 4 0 14 -- 12 12 -- -- -- -- 12 12 26 4 0 0 14 20 12 12 13 40 TH + 34 19 12 12 14 -- 12 12 -- -- -- -- 12 12
115 Data input valid to SCKR edge (data input setup time) 116 SCKR edge to data input not valid (data input hold time)
IN
Master Slave Master Slave Master Slave Slave Master Slave1 Slave2 Master Slave Slave
IM
117 SCKR edge to word select output valid (WSR out delay time) 118 Word select input valid to SCKR edge (WSR in setup time) 119 SCKR edge to word select input not valid (WSR in hold time) 121 SCKT edge to data output valid (data out delay time)
EL PR
122 SCKT edge to word select output valid (WST output delay time) 123 Word select input valid to SCKT edge (WST in setup time) 124 SCKT edge to word select input not valid (WST in hold time)
Notes: 1. 2.
When the Frequency Ratio between Parallel and Serial clocks is 1:4 or greater When the Frequency Ratio between Parallel and Serial clocks is 1:3 - 1:4
Preliminary Information MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 2-13
Y
-- 36.5 13 -- ns 16.7 -- -- ns -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -- 8 5.5 -- -- -- -- 20 -- -- 13 40 39.25 19 -- --
Specifications Serial Audio Interface (SAI) Timing)
111 112 SCKR (RCKP = 1) 111 113 SCKR (RCKP = 0) 115 SDI0-SDI1 (Data Input) 118 WSR (Input) 116 114 113 114
IN
Valid
IM
WSR (Output)
AR
Valid 119 117
AA0269
112
Figure 2-13 SAI Receiver Timing
PR
Preliminary Information 2-14 DSP56011 Technical Data Sheet, Rev. 1 MOTOROLA
EL
Y
114
114
Specifications Serial Audio Interface (SAI) Timing)
111 112 SCKT (TCKP = 1) 111 113 SCKT (TCKP = 0) 121 SDO0-SDO2) (Data Output) 123 WST (Input) 114 113 114
IN
Valid
IM
WST (Output)
AR
124 122
AA0270
112
Figure 2-14 SAI Transmitter Timing
PR
Preliminary Information MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 2-15
EL
Y
114
114
Specifications Serial Host Interface (SHI) SPI Protocol Timing
SERIAL HOST INTERFACE (SHI) SPI PROTOCOL TIMING
Table 2-10 Serial Host Interface (SHI) SPI Protocol Timing
No. Characteristics Mode Filter Mode Bypassed Narrow Wide 81 MHz Expression Min Max Min Max -- -- -- 0 20 100 -- -- -- 0 20 100 95 MHz Unit ns ns ns
* *
Frequency below 33 MHz1
Master
Bypassed Bypassed Narrow Wide
AR
4 x TC 6 x TC 1000 2000 -- -- -- 74.1 -- 63 1000 -- 1000 2000 37 62 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2000 31.5 56.5 116.5 110.5 462.5 1053.5 21.5 18.5 41.5 53.5 55.75 231.75 526.75 21.5 18.5 41.5 53.5 55.75 231.75 526.75 3 x TC 3 x TC + 25 3 x TC + 79 3 x TC + 431 3 x TC + 85 122 116 468 1059 3 x TC + 1022 TC + 8 TC + 31 TC + 43 TC + TH + 40 TC + TH + 216 TC + TH + 511 TC + 8 TC + 31 TC + 43 TC + TH + 40 TC + TH + 216 TC + TH + 511 0.5 x TSPICC -10 27.0 20.3 43.3 55.3 58.5 235 536 0.5 x TSPICC -10 27.0 20.3 43.3 55.3 58.5 235 536
141 Minimum Serial Clock cycle = tSPICC(min)
Frequency above Master 33 MHz1
IN
Bypassed Narrow Wide Bypassed Narrow Wide Bypassed Narrow Wide Bypassed Narrow Wide Bypassed Narrow Wide Bypassed Narrow Wide
CPHA = 0, CPHA =
12
Slave
CPHA = 1
IM
Slave Master Slave Slave Master Slave 12 Slave
142 Serial Clock high period CPHA = 0, CPHA = 12
EL
CPHA = 1 143 Serial Clock low period CPHA = 0, CPHA = CPHA = 1
PR
Preliminary Information 2-16 DSP56011 Technical Data Sheet, Rev. 1 MOTOROLA
Y
-- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Tolerable spike width on Clock or Data input
Specifications Serial Host Interface (SHI) SPI Protocol Timing
Table 2-10 Serial Host Interface (SHI) SPI Protocol Timing (Continued)
No. Characteristics Mode Master Slave Slave Bypassed Narrow Wide CPHA = 1 Slave Filter Mode 81 MHz Expression Min Max Min Max 10 2000 TC + TH + 35 TC + TH + 35 TC + TH + 35 6 0 -- -- 53.5 53.5 53.5 6 10 2000 -- -- -- -- -- 50.75 50.75 50.75 6 10 2000 -- -- -- ns ns ns ns ns 95 MHz Unit
144 Serial Clock rise/fall time 146 SS assertion to first SCK edge CPHA = 0
Bypassed Narrow Wide
AR
-- 0 0 -- -- 0 0 0 TC + 6 18.3 82.4 209 2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 16.5 80.5 TC + 70 2 TC + 197 66 207.5 2 66 193 0 26.5 41.5 0 27.5 42.5 38 39 49 38 39 49 4 66 193 0 193 0 25 40 0 26 41 41.7 42.7 52.7 41.7 42.7 52.7 4 MAX {(37 -TC), 0} MAX {(52 -TC), 0} 0 MAX {(38 -TC), 0} MAX {(53 -TC), 0} 2 x TC + 17 2 x TC + 18 2 x TC + 28 2 x TC + 17 2 x TC + 18 2 x TC + 28 4
IN
Wide Bypassed Narrow Wide Bypassed Narrow Wide Bypassed Narrow Wide Bypassed Narrow Wide Bypassed Narrow Wide
147 Last SCK edge to SS not asserted CPHA = 0 CPHA = 13
Slave
Bypassed Narrow
Slave
148 Data input valid to SCK edge (data input setup time)
IM
Master Slave Master Slave Slave
EL PR
149 SCK edge to data input not valid (data in hold time) 150 SS assertion to data out active
Preliminary Information MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 2-17
Y
-- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Specifications Serial Host Interface (SHI) SPI Protocol Timing
Table 2-10 Serial Host Interface (SHI) SPI Protocol Timing (Continued)
No. Characteristics Mode Slave Master Bypassed Narrow Wide CPHA = 0, CPHA = 12 Slave Bypassed Narrow Wide CPHA = 1 Slave Filter Mode 81 MHz Expression Min Max Min Max 24 41 214 504 41 -- -- -- 24 41 214 -- -- -- 24 41 214 ns ns ns 95 MHz Unit
151 SS deassertion to data tri-stated4 152 SCK edge to data out valid (data out delay time)
AR
-- 41 -- 214 -- 214 -- 504 -- 504 -- TC + TH + 40 -- -- -- 0 58.5 235 536 -- -- -- -- -- -- 53.5 -- -- -- 0 57 163 0 57 163 -- TC + TH + 216 TC + TH + 511 0 57 57 163 0 57 163 TC + TH + 35 163 0 57 163 -- -- -- -- 75 252 550 -- -- -- -- -- -- -- 32.25 89.25 195.25 33.25 3 x TC + TH + 209 3 x TC + TH + 507 2 x TC + TH + 6 36.9 2 x TC + TH + 63 93.9 2 x TC + TH + 169 200 2 x TC + TH + 7 37.9
Bypassed Narrow Wide
IN
Bypassed Narrow Wide Bypassed Narrow Wide Bypassed 3 x TC + TH + 32 Narrow Wide Bypassed Narrow Wide
153 SCK edge to data out not Master valid (data out hold time) Slave
IM
Slave Slave Slave Slave
EL
157 First SCK sampling edge to HREQ output deassertation 158 Last SCK sampling edge to HREQ output not deasserted CPHA = 1 159 SS deassertion to HREQ output not deasserted CPHA = 0
154 SS assertion to data output valid CPHA = 0
PR
Preliminary Information 2-18 DSP56011 Technical Data Sheet, Rev. 1 MOTOROLA
Y
-- 504 -- 504 41 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 214 504 55.75 231.75 536 -- -- -- -- -- -- 50.75 68.75 245.75 543.75 -- -- -- -- ns ns ns ns ns ns ns
Specifications Serial Host Interface (SHI) SPI Protocol Timing
Table 2-10 Serial Host Interface (SHI) SPI Protocol Timing (Continued)
No. Characteristics Mode Slave Filter Mode 81 MHz Expression Min Max Min Max TC + 4 16.3 -- 14.5 -- ns 95 MHz Unit
160 SS deassertion pulse width CPHA = 0 161 HREQ input assertion to first SCK edge
163 First SCK edge to HREQ input not asserted (HREQ input hold time)
Notes: 1.
Master
AR
0 0 -- 0
162 HREQ input deassertion Master to last SCK sampling edge (HREQ input setup time) CPHA = 1
0
2.
3. 4.
PR
MOTOROLA
EL
Preliminary Information DSP56011 Technical Data Sheet, Rev. 1 2-19
IM
For an internal clock frequency below 33 MHz, the minimum permissible internal clock to SCK frequency ratio is 4:1. For an internal clock frequency above 33 MHz, the minimum permissible internal clock to SCK frequency ratio is 6:1. In CPHA = 1 mode, the SPI slave supports data transfers at TSPICC = 3 x TC, if the user assures that the HTX is written at least TC ns before the first edge of SCK of each word.In CPHA = 1 mode, the SPI slave supports data transfers at TsPICC = 3 x TC, if the user assures that the HTX is written at least TC ns before the first edge of SCK of each word. When CPHA = 1, the SS line may remain active low between successive transfers. Periodically sampled, not 100% tested
IN
Y
0 -- 0 -- ns -- ns
Master
0.5 x TSPICC+ 2 x TC + 6
67.7
--
58.5
--
ns
Specifications Serial Host Interface (SHI) SPI Protocol Timing
SS (Input) 143 142 SCK (CPOL = 0) (Output) 142 143 SCK (CPOL = 1) (Output) 148 MISO (Input)
MSB Valid
141 144 144
149
152 MOSI (Output) 161 HREQ (Input) MSB
IM
2-20
IN
163
AR
148 149
LSB Valid
Figure 2-15 SPI Master Timing (CPHA = 0)
PR
EL
Preliminary Information DSP56011 Technical Data Sheet, Rev. 1 MOTOROLA
Y
144 153 LSB
AA0271
144
141
Specifications Serial Host Interface (SHI) SPI Protocol Timing
SS (Input) 143 142 SCK (CPOL = 0) (Output) 142 143 SCK (CPOL = 1) (Output) 149 MISO (Input)
MSB Valid
141 144 144
141
152 MOSI (Output) 161 HREQ (Input) MSB
IM PR
MOTOROLA
IN
162 163
AR
LSB Valid
148
Figure 2-16 SPI Master Timing (CPHA = 1)
EL
Preliminary Information DSP56011 Technical Data Sheet, Rev. 1 2-21
Y
144 148 149 153 LSB
AA0272
144
Specifications Serial Host Interface (SHI) SPI Protocol Timing
SS (Input) 143 142 SCK (CPOL = 0) (Input) 143 SCK (CPOL = 1) (Input) 154 150 MISO (Output) 148 149 MOSI (Input) HREQ (Output)
MSB Valid
141 144 144 160
147
144
153 MSB
157
IN
Preliminary Information
IM
AR
152 153 151 LSB 148 149
LSB Valid
Figure 2-17 SPI Slave Timing (CPHA = 0)
PR
2-22
EL
DSP56011 Technical Data Sheet, Rev. 1 MOTOROLA
Y
144 159
AA0273
146
142
141
Specifications Serial Host Interface (SHI) SPI Protocol Timing
SS (Input) 143 142 SCK (CPOL = 0) (Input) 143 SCK (CPOL = 1) (Input) 152 150 MISO (Output) 148 MOSI (Input) HREQ (Output)
MSB Valid
141 144 144
147
144
152 MSB
IN
157
IM
AR
153 151 LSB 148 149 149
LSB Valid
Figure 2-18 SPI Slave Timing (CPHA = 1)
PR
MOTOROLA
EL
Preliminary Information DSP56011 Technical Data Sheet, Rev. 1 2-23
Y
144 158
AA0274
146
142
Specifications Serial Host Interface (SHI) I2C Protocol Timing
SERIAL HOST INTERFACE (SHI) I2C PROTOCOL TIMING
RP (min) = 1.5 k Table 2-11 SHI I2C Protocol Timing
Standard I2C (CL = 400 pF, RP = 2 k, 100 kHz) No. Characteristics Tolerable spike width on SCL or SDA filters bypassed Narrow filters enabled Wide filters enabled 171 172 173 174 175 176 177 178 179 Minimum SCL Serial Clock cycle Bus free time Symbol
AR
-- 0 -- 20 -- 100 -- -- -- -- -- -- 1.0 0.3 -- -- 3.4 -- TSCL 10.0 4.7 4.7 4.0 4.7 4.0 -- -- 250 0.0 -- 4.0 TBUF TSU;STA THD;STA TLOW THIGH TR TF TSU;DAT THD;DAT TVD;DAT TSU;STO
IN
Preliminary Information
Start condition setup time Start condition hold time SCL low period
IM
SCL high period
SCL and SDA rise time SCL and SDA fall time Data setup time
EL
180 Data hold time 182 183 SCL low to data output valid Stop condition setup time
PR
2-24
DSP56011 Technical Data Sheet, Rev. 1
Y
All Frequencies Min Max Unit ns ns ns s s s s s s s s ns ns s s
MOTOROLA
Specifications Serial Host Interface (SHI) I2C Protocol Timing
Programming the Serial Clock
The Programmed Serial Clock Cycle, t I2CCP , is specified by the value of the HDM5- HDM0 and HRS bits of the HCKR (SHI Clock control Register). The expression for t I2CCP is:
t I2CCP = [TC x 2 x (HDM[5:0] + 1) x (7 x (1 - HRS) + 1)]
where -
- -
MDM5-HDM0 are the Divider Modulus Select bits.
A divide ratio from 1 to 64 (HDM5-HDM0 = 0 to $3F) may be selected.
6 x TC (if HDM[5:0] = $02 and HRS = 1) to 1024 x TC (if HDM[5:0] = $3F and HRS = 0)
PR
Preliminary Information MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 2-25
EL
IM
The DSP56011 provides an improved I2C bus protocol. In addition to supporting the 100 kHz I2C bus protocol, the SHI in I2C mode supports data transfers at up to 1000 kHz. The actual maximum frequency is limited by the bus capacitances (CL),the pullup resistors (RP), (which affect the rise and fall time of SDA and SCL, see Table 2-12 on page 2-26), and by the input filters.
IN
In I2C mode, you may select a value for the Programmed Serial Clock Cycle from:
AR
HRS is the Prescaler Rate Select bit. When HRS is cleared, the fixed divideby-eight prescaler is operational. When HRS is set, the prescaler is bypassed.
Y
Specifications Serial Host Interface (SHI) I2C Protocol Timing
Considerations for Programming the SHI Clock Control Register (HCKR)--Clock Divide Ratio
The master must generate a bus free time greater than T172 slave when operating with a DSP56011 SHI I2C slave. Table 2-12 describes a few examples. Table 2-12 Considerations for Programming the SHI Clock control Register (HCKR)
Conditions to be Considered Master Operating Freq. 81 MHz Slave Operating Freq. 81 MHz Master Filter Mode Bypassed Narrow Wide Bypassed Narrow Wide Slave Filter Mode
Bus Load
CL = 50 pF, RP = 2 k CL = 50 pF, RP = 2 k
Bypassed 36 ns Narrow 60 ns Wide 95 ns Bypassed 32 ns Narrow 56 ns Wide 91 ns
95 MHz
95 MHz
IN
Preliminary Information
PR
2-26
EL
In general, bus performance may be calculated from the CL and RP of the bus, the input filter modes and operating frequencies of the master and the slave. Table 2-13 on page 2-27 contains the expressions required to calculate all relevant performance timing for a given CL and RP. Note: T177 (tr) is computed using the values of CL and RP and T178 (TF) is computed using the value of CL. The two values are used in computing many of the other timing values in Table 2-13 on page 2-27.
IM
Example: for CL = 50 pF, RP = 2 k, f = 81 MHz, Bypassed filter mode: The master, when operating with a DSP56011 SHI I2C slave with an 81 MHz operating frequency, must generate a bus free time greater than 36 ns (T172 slave). Thus, the minimum permissible TI2CCP is 52 x TC, which gives a bus free time of at least 41 ns (T172 master). This implies a maximum I2C serial frequency of 1010 kHz.
DSP56011 Technical Data Sheet, Rev. 1
AR
T172 Slave T172 Master 41 ns 66 ns 103 ns
2
Y
Resulting Limitations Min. Permissible tI CCP Maximum I2C Serial Frequency 1010 kHz 825 kHz 634 kHz 1030 kHz 843 kHz 645 kHz 52 x TC 56 x TC 62 x TC 60 x TC 64 x TC 71 x TC 35 ns 56 ns 92.8 ns
MOTOROLA
Specifications Serial Host Interface (SHI) I2C Protocol Timing
Table 2-13 SHI Improved I2C Protocol Timing
Improved I2C (CL = 50 pF, RP = 2 k) Filter Mode Bypassed Narrow Wide TSCL Master Bypassed Narrow Wide Slave
2
81 MHz2 Expression
95 MHz3 Unit Max 0 20 100 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns
No.
Characteristic
Sym.
Mode
Min Max Min 0 20 100 -- -- -- 0 20 100 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
AR
T I CCP + 3 x TC + 245 + TR
2
171 SCL Serial Clock cycle
T I CCP + 3 x TC + 72 +TR
T I CCP + 3 x TC + 535 + TR
2
IN
Narrow Wide 172 Bus free time
Bypassed 4 x TC + TH + 172 + 466 TR 4 x TC + TH + 366 + 660 TR 4 x TC + TH + 648 + 942 TR
2
IM
TBUF Narrow Wide Slave Bypassed Narrow Wide Bypassed Narrow Wide TSU;STA Slave Narrow Wide Slave Bypassed Narrow Wide
Master Bypassed 0.5 x T I CCP - 42 - TR 41.1 0.5 x T I CCP - 42 - TR 65.8
2
0.5 x T I CCP - 42 - TR 103
2
EL
2 x TC + 11 2 x TC + 35 2 x TC + 70 12 50 150
2
PR
173 Start condition setup time
174 Start condition hold time
THD;STA Master Bypassed 0.5 x T I CCP + 12 - TF 313 0.5 x T I CCP + 12 - TF 338
2
0.5 x T I CCP + 12 - TF 375
2
2 x TC + TH + 21 2 x TC + TH + 100 2 x TC + TH + 200
Preliminary Information MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 2-27
Y
989 971.5 1212 1576 1186.5 1550 457.3 651.3 933.3 35 56 92.8 32 56 91 12 50 150 307 328 364.8 47.25 126.25 226.25 35.7 59.7 94.7 12 50 150 51.9 131 231
-- Tolerable spike width on SCL or SDA
ns ns ns ns ns ns ns ns ns
ns ns ns ns ns ns ns ns ns ns ns ns
Specifications Serial Host Interface (SHI) I2C Protocol Timing
Table 2-13 SHI Improved I2C Protocol Timing (Continued)
Improved I2C (CL = 50 pF, RP = 2 k) Filter Mode 81 MHz2 Expression Min Max Min
2
95 MHz3 Unit Max -- -- -- -- -- -- -- -- -- -- -- -- 238 2000 20 2000 -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
No.
Characteristic
Sym. TLOW
Mode
175 SCL low period
Narrow Wide Slave Bypassed Narrow Wide 176 SCL high period THIGH
0.5 x T I CCP + 18 - TF 344
2
IN
Narrow Wide
2 2
Master Bypassed 0.5 x T I CCP +2 x TC 365 + 19
2
IM
Narrow Wide TR TF TSU;DAT Bypassed Narrow Wide Bypassed Narrow Wide THD;DAT
Slave
Bypassed
177 SCL rise time Output Input
EL
Input
178 SCL fall time Output
PR
179 Data setup time 180 Data hold time
Preliminary Information 2-28 DSP56011 Technical Data Sheet, Rev. 1 MOTOROLA
AR
2 x TC + 74 + TR 337 -- -- -- 333 545 845 2 x TC + 286 + TR 548.6 849 2 x TC + 586 + TR -- 355 0.5 x T I CCP +2 x TC 514 + 144 -- -- -- -- -- 238 2000 20 2000 -- -- -- -- -- -- 501 749.8 25.25 44.25 56.25 -- -- -- -- 18.5 70.5 84.5 0 0 0 0.5 x T I CCP + 2 x TC 763 + 356 2 x TC + TH - 1 30 49 61 -- -- -- -- 20 72 86 0 0 0 2 x TC + TH + 18 2 x TC + TH + 30 1.7 x RP x (CL + 20)1 2000 20 + 0.1 x (CL- 50)1 2000 TC + 8 TC + 60 TC + 74 0 0 0
0.5 x T I CCP + 18 - TF 381
2
Y
-- -- 334 370.75
Master Bypassed 0.5 x T I CCP + 18 - TF 319
--
313
Specifications Serial Host Interface (SHI) I2C Protocol Timing
Table 2-13 SHI Improved I2C Protocol Timing (Continued)
Improved I2C (CL = 50 pF, RP = 2 k) Filter Mode Bypassed Narrow Wide 183 Stop condition setup time TSU;STO Master Bypassed Narrow Wide Slave 81 MHz2 Expression Min Max Min 2 x TC + 71 + TR -- -- -- 334 507 798 -- -- -- -- -- -- Max 330 503 794 -- -- -- -- -- -- -- -- -- 68.75 ns ns ns 95 MHz3 Unit
No.
Characteristic
Sym. TVD;DAT
Mode
2 x TC + 244 + TR 2 x TC + 535 + TR
2
AR
0.5 x T I CCP + TC + TH + 11
2
0.5 x T I CCP + TC + TH + 69 0.5 x T I CCP + TC + TH + 183
2
IN
Bypassed Narrow Wide 11 50 150 0 0 0
IM
Narrow Wide Slave Bypassed Narrow Wide Bypassed Narrow Wide Master Bypassed Narrow Wide Master Slave
184 HREQ input deassertion to last SCL edge (HREQ in setup time)
Master Bypassed
EL
186 First SCL sampling edge to HREQ output deassertation
3 x TC + TH + 32
3 x TC + TH + 209 3 x TC + TH + 507 2 x TC + TH + 6 2 x TC + TH + 63 2 x TC + TH + 169 T I CCP + 2 x TC + 6
2
PR
187 Last SCL edge to HREQ output not deasserted 188 HREQ input assertion to first SCL edge
T I CCP + 2 x TC + 6
2
T I CCP + 2 x TC + 6
2
189 First SCL edge to HREQ input not asserted (HREQ input hold time)
0
Preliminary Information MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 2-29
Y
351 433 584 11 50 150 0 0 0 -- -- -- 37 93.9 200 673 722 796 0 341.75 420.75 571.5 11 50 150 0 0 0 -- -- -- 32.25 89.25 195.25 657 699 772.5 0 -- -- -- -- -- -- 75 252 550 -- -- -- -- -- -- -- 543.7 -- -- -- -- -- -- --
182 SCL low to data output valid
ns ns ns ns ns ns ns ns ns ns
245.75 ns ns ns ns ns ns ns ns ns
Specifications Serial Host Interface (SHI) I2C Protocol Timing
Table 2-13 SHI Improved I2C Protocol Timing (Continued)
Improved I2C (CL = 50 pF, RP = 2 k) Filter Mode 81 MHz2 Expression Min Max Min Max 95 MHz3 Unit
No.
Notes:
Characteristic
1. 2.
Sym.
Mode
3.
2
2
2
171 173 SCL 177 172 SDA
Stop Start
176
IM
MSB
IN
175 178 180 179
LSB ACK Stop
174 188
186
189
EL
HREQ
AR
182 184 187 183
CL is in pF, RP is in k, and result is in ns. A T I CCP of 52 x TC (the maximum permitted for the given bus load) was used for the calculations in the Bypassed filter mode. A T I CCP of 56 x TC (the maximum permitted for the given bus load) was used for the calculations in the Narrow filter mode. A T I CCP of 62 x TC (the maximum permitted for the given bus load) was used for the calculations in the Wide filter mode. A T I CCP of 60 x TC (the maximum permitted for the given bus load) was used for the calculations in the Bypassed filter mode. A T I CCP of 64 x TC (the maximum permitted for the given bus load) was used for the calculations in the Narrow filter mode. A T I CCP of 71 x TC (the maximum permitted for the given bus load) was used for the calculations in the Wide filter mode.
2 2 2
Figure 2-19 I2C Timing
PR
Preliminary Information 2-30 DSP56011 Technical Data Sheet, Rev. 1 MOTOROLA
Y
AA0275
Specifications General Purpose Input/Output (GPIO) Timing
GENERAL PURPOSE INPUT/OUTPUT (GPIO) TIMING
Table 2-14 GPIO Timing
All Frequencies No. Characteristics Expression Min 201 202 203 204 EXTAL edge to GPIO output valid (GPIO output delay time) EXTAL edge to GPIO output not valid (GPIO output hold time) 26 2 -- 2 Max 26 ns Unit
GPIO input valid to EXTAL Edge (GPIO input setup time)
AR
10 6 10 6 -- -- 201 202 204
EXTAL edge to GPIO input not valid (GPIO input hold time)
EXTAL (Input) (see Note)
GPIO0-GPIO7 PB0-PB14 (Output)
EL
Note:
GPIO0-GPIO7 PB0-PB14 (Input)
Valid when the ratio between EXTAL frequency and internal clock frequency equals 1
AA1284
PR
MOTOROLA
IM
203 Valid
DSP56011 Technical Data Sheet, Rev. 1
IN
Figure 2-20 GPIO Timing
Preliminary Information 2-31
Y
-- ns ns ns
Specifications Digital Audio Transmitter (DAX) Timing
DIGITAL AUDIO TRANSMITTER (DAX) TIMING
Table 2-15 56011 Digital Audio Transmitter Timing
All Frequencies No. Characteristic Min ACI Frequency (see Note) 220 221 222 223
Note:
Unit Max 25 MHz ns
ACI Period ACI High Duration ACI Low Duration ACI Rising Edge to ADO Valid
AR
-- -- 0.5 x TC -- 35 221 222
0.5 x TC
ACI
ADO
IM
220 223
IN
Preliminary Information
In order to assure proper operation of the DAX, the ACI frequency should be less than 1/2 of the DSP56011 internal clock frequency. For example, if the DSP56011 is running at 40 MHz internally, the ACI frequency should be less than 20 MHz.
PR
2-32
EL
Figure 2-21 Digital Audio Transmitter Timing
DSP56011 Technical Data Sheet, Rev. 1
Y
40 -- ns ns ns
AA1280
--
MOTOROLA
Specifications On-Chip Emulation (OnCETM) Timing
ON-CHIP EMULATION (OnCETM) TIMING
Table 2-16 OnCE Timing
All Frequencies No. 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 DSCK low DSCK high DSCK cycle time DR asserted to DSO (ACK) asserted DSCK high to DSO valid DSCK high to DSO invalid DSI valid to DSCK low (setup) DSCK Low to DSI Invalid (Hold) Last DSCK low to OS0-OS1, ACK active DSO (ACK) asserted to first DSCK high DSO (ACK) assertion width Characteristics Min 40 40 Max -- -- ns ns Unit
200
AR
5 TC -- 3 -- 42 -- -- 15 3 -- 3 TC + TL 2 TC -- -- -- 5 TC + 7 0 -- -- -- -- TC - 10 -- 4 TC + TH - 3 TC - 21 0 7 TC + 10 3 10 17 TC 15 13 TC + 15 17 TC 12 TC - 15 -- --
IN
Preliminary Information
OS0-OS1 valid to second EXTAL transition
IM
DSO (ACK) asserted to OS0-OS1 high impedance1
Second EXTAL transition to OS0-OS1 invalid
Last DSCK low of read register to first DSCK high of next command Last DSCK low to DSO invalid (hold)
EL
247 248
DR assertion to second EXTAL transition for wake up from Wait state Second EXTAL transition to DSO after wake up from Wait state DR assertion width * To recover from Wait * To recover from Wait and enter Debug mode
PR
249
DR assertion to DSO (ACK) valid (enter Debug mode) after asynchronous recovery from Wait state
MOTOROLA
DSP56011 Technical Data Sheet, Rev. 1
Y
-- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2-33
Specifications On-Chip Emulation (OnCETM) Timing
Table 2-16 OnCE Timing (Continued)
All Frequencies No. Characteristics Min 250A DR assertion width to recover from Stop2 * Stable External Clock, OMR Bit 6 = 0 * Stable External Clock, OMR Bit 6 = 1 * Stable External Clock, PCTL Bit 17 = 1 250B DR assertion width to recover from Stop and enter Debug mode2 * Stable External Clock, OMR Bit 6 = 0 * Stable External Clock, OMR Bit 6 = 1 * Stable External Clock, PCTL Bit 17= 1 DR assertion to DSO (ACK) valid (enter Debug mode) after recovery from Stop state2 * Stable External Clock, OMR Bit 6 = 0 * Stable External Clock, OMR Bit 6 = 1 * Stable External Clock, PCTL Bit 17= 1
1. 2. Maximum TL Periodically sampled, not 100% tested
Unit Max 65548 TC + TL 20 TC + TL 13 TC + TL ns
251
AR
65553 TC + TL 25 TC + TL 18 TC + TL -- -- -- 246 231 232 240
ACK
65549 TC + TL 21 TC + TL 14 TC + TL
Notes:
DSCK (input)
IM
230 233
IN
246
PR
EL
DR (Input) DSO (Output)
Figure 2-22 DSP56011 OnCE Serial Clock Timing
Figure 2-23 DSP56011 OnCE Acknowledge Timing
Preliminary Information 2-34 DSP56011 Technical Data Sheet, Rev. 1 MOTOROLA
Y
ns -- -- -- ns
AA0277 AA0278
15 15 15
Specifications On-Chip Emulation (OnCETM) Timing
DSCK (Input) DSO (Output) 236 DSI (Input) Note: High Impedance, external pull-down resistor 237
(Last)
(OS1)
238
(ACK) (OS0)
DSCK (Input) 234 DSO (Output) Note: 235
High Impedance, external pull-down resistor
IN
239 (see Note) 240 (see Note) 236
AR
(Last) 245 (OS0) (DSCK Input) (DSO Output) (DSI Input) 237
Figure 2-24 DSP56011 OnCE Data I/O to Status Timing
Figure 2-25 DSP56011 OnCE Read Timing
OS1 (Output)
DSO (Output)
PR
EL
OS0 (Output) 241 Note:
High Impedance, external pull-down resistor
IM
241
Figure 2-26 DSP56011 OnCE Data I/O Status Timing
Preliminary Information MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 2-35
Y
(Note 1) (Note 1)
AA0279
AA0280
AA1281
Specifications On-Chip Emulation (OnCETM) Timing
EXTAL (Note 2) 242 OS0-OS1 (Output) (Note 1) Note: 243
DSCK (Input)
AR
244 248 247 248 249
Figure 2-27 DSP56011 OnCE EXTAL to Status Timing
Figure 2-28 DSP56011 OnCE DSCK Next Command After Read Register Timing
T0, T2 T1, T3
EXTAL
DR (Input)
EL
DR (Input) DSO (Output)
DSO (Output)
IM
246
IN
Preliminary Information
Figure 2-29 Synchronous Recovery from Wait State
PR
Figure 2-30 Asynchronous Recovery from Wait State
2-36
DSP56011 Technical Data Sheet, Rev. 1
Y
(Next Command)
1. High Impedance, external pull-down resistor 2. Valid when the ratio between EXTAL frequency and clock frequency equals 1
AA0282
AA0283
AA0284
AA0285
MOTOROLA
Specifications On-Chip Emulation (OnCETM) Timing
250 DR (Input) 251 DSO (Output)
Figure 2-31 Asynchronous Recovery from Stop State
PR
MOTOROLA
EL
Preliminary Information DSP56011 Technical Data Sheet, Rev. 1 2-37
IM
IN
AR
Y
AA0286
Specifications On-Chip Emulation (OnCETM) Timing
PR
Preliminary Information 2-38 DSP56011 Technical Data Sheet, Rev. 1 MOTOROLA
EL
IM
IN
AR
Y
SECTION PACKAGING
PIN-OUT AND PACKAGE INFORMATION
3
PR
Preliminary Information MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 3-1
EL
IM
IN
AR
This sections provides information about the available packages for this product, including diagrams of the package pinouts and tables describing how the signals described in Section 1 are allocated. The DSP56011 is available in a 100-pin Thin Quad Flat Pack (TQFP) package.
Y
Packaging Pin-out and Package Information
TQFP Package Description
Top and bottom views of the TQFP package are shown in Figure 3-1 and Figure 3-2 with their pin-outs.
DR not connected not connected not connected not connected DSCK/OS1 DSI/OS0 DSO SDI0 SDI1 WSR GNDS VCCQ GNDQ SCKR WST SCKT VCCS SDO0 SDO1 SDO2 GNDS HREQ SS/HA2 MOSI/HA0 75 GPIO7 GPIO6 GNDD GPIO5 GPIO4 VCCD GPIO3 GPIO2 GNDD GPIO1 GPIO0 GNDQ VCCQ not connected not connected GNDA not connected VCCA not connected not connected GNDA not connected not connected not connected VCCA 76
EL
100 1
IM
Orientation Mark
not connected not connected GNDA not connected not connected H7/PB7 H6/PB6 GNDH HOA2/PB10 VCCH HOA1/PB9 HR/W/PB11 HEN/PB12 VCCQ GNDQ HACK/PB14 GNDH HOA0/PB8 H5/PB5 VCCH H4/PB4 H3/PB3 GNDH H2/PB2 H1/PB1 25
IN
(Top View)
26
PR
AR
50
51
Figure 3-1 DSP56011 Thin Quad Flat Pack (TQFP), Top View
Preliminary Information 3-2 DSP56011 Technical Data Sheet, Rev. 1 MOTOROLA
Y
VCCS MODC/NMI MODB/IRQB MODA/IRQA RESET MISO/SDA GNDS SCK/SCL EXTAL VCCP PCAP GNDP PINIT GNDQ VCCQ PLOCK not connected not connected not connected ACI ADO VCCH GNDH HOREQ/PB13 H0/PB0 AA1282
Packaging Pin-out and Package Information
MOSI/HA0 SS/HA2 HREQ GNDS
51
IM
25 26
VCCS MODC/NMI MODB/IRQB MODA/IRQA RESET MISO/SDA GNDS SCK/SCL EXTAL VCCP PCAP GNDP PINIT GNDQ VCCQ PLOCK not connected not connected not connected ACI ADO VCCH GNDH HOREQ/PB13 H0/PB0
75
WSR SDI1 SDI0 DSO DSI/OS0 DSCK/OS1 not connected not connected not connected not connected DR
SCKT WST SCKR GNDQ VCCQ GNDS
SDO2 SDO1 SDO0 VCCS
50
76
Orientation Mark
(Bottom View)
100 1
GPIO7 GPIO6 GNDD GPIO5 GPIO4 VCCD GPIO3 GPIO2 GNDD GPIO1 GPIO0 GNDQ VCCQ not connected not connected GNDA not connected VCCA not connected not connected GNDA not connected not connected not connected VCCA
EL PR
MOTOROLA
H1/PB1 H2/PB2 GNDH H3/PB3 H4/PB4 VCCH H5/PB5 HOA0/PB8 GNDH HACK/PB14 GNDQ VCCQ HEN/PB12 HR/W/PB11 HOA1/PB9 VCCH HOA2/PB10 GNDH H6/PB6 H7/PB7 not connected not connected GNDA not connected not connected
IN
Preliminary Information
AR
DSP56011 Technical Data Sheet, Rev. 1
Figure 3-2 DSP56011 Thin Quad Flat Pack (TQFP), Bottom View
Y
AA1283
3-3
Packaging Pin-out and Package Information
Table 3-1 Signal by Pin Number
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Signal Name not connected not connected GNDA not connected not connected H7/PB7 H6/PB6 GNDH HOA2/PB10 VCCH HOA1/PB9 HR/W/PB11 HEN/PB12 VCCQ Pin # 26 27 28 29 30 31 32 33 34 35 36 37 38 Signal Name H0/PB0 HOREQ/ PB13 GNDH VCCH ADO ACI Pin # 51 52 53 54 55 Signal Name MOSI/HA0 SS/HA2 HREQ GNDS SDO2 Pin # 76 77 78 Signal Name GPIO7 GPIO6 GNDD
not connected not connected
IN
PLOCK VCCQ 60 WST 61 62 SCKR GNDQ PINIT GNDQ VCCQ GNDS WSR SDI1 SDI0 DSO DSI/OS0 DSCK/OS1 not connected not connected not connected not connected DR 63 GNDP PCAP VCCP 64 65 66 67 68 69 70 71 72 73 74 75 EXTAL SCK/SCL GNDS MISO/SDA RESET MODA/ IRQA MODB/IRQB MODC/NMI VCCS
not connected
IM
39 40 41 42 43 44 45 46 47 48 49 50
GNDQ
HACK/PB14 GNDH
EL
18 HOA0/PB8 H5/PB5 VCCH 19 20 21 H4/PB4 22 H3/PB3 GNDH 23 24 25 H2/PB2 H1/PB1
PR
Preliminary Information 3-4 DSP56011 Technical Data Sheet, Rev. 1 MOTOROLA
AR
80 56 SDO1 81 57 SDO0 VCCS 82 58 83 59 SCKT 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Y
79 GPIO5 GPIO4 VCCD GPIO3 GPIO2 GNDD GPIO1 GPIO0 GNDQ VCCQ not connected not connected GNDA not connected VCCA not connected not connected GNDA not connected not connected not connected VCCA
Packaging Pin-out and Package Information
Table 3-2 Signal by Name
Signal Name ACI ADO DR DSCK DSI DSO EXTAL GNDA GNDA GNDA GNDD GNDD GNDH GNDH GNDH GNDH GNDP GNDQ GNDQ GNDQ GNDQ GNDS GNDS GNDS Pin # 31 30 75 70 69 68 42 3 91 96 78 84 8 17 23 28 39 15 37 62 87 44 64 54 Signal Name GPIO7 H0 H1 H2 H3 H4 H5 H6 H7 HA0 HA2 Pin # 76 26 25 24 22 21 19 7 6 51 52 Signal Name not connected not connected not connected not connected not connected not connected not connected Pin # 32 33 34 71 72 Signal Name PB14 PCAP PINIT PLOCK RESET SCK Pin # 16 40 38 35
AR
73 74 SCKR SCKT SCL not connected not connected 89 90 not connected 92 SDA not connected 94 95 97 SDI0 SDI1 SDO0 SDO1 SDO2 SS VCCA VCCA VCCD VCCH VCCH VCCH VCCP VCCQ VCCQ VCCQ VCCQ VCCS VCCS WSR WST not connected not connected not connected not connected OS0 OS1 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 98 99 69 70 26 25 24 22 21 19 7 6 18 11 9 12 13 27
IN
16 13 18 11 9 27 53 12 47 48 45 47 48 49 51 49 1 2 4 5
HACK HEN
HOA0 HOA1 HOA2
IM
HOREQ HREQ HR/W IRQA IRQB MISO MODA MODB MODC MOSI NMI not connected not connected not connected not connected 86 85 83 82 80 79 77
EL PR
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6
Preliminary Information MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 3-5
Y
46 43 61 59 43 45 67 66 57 56 55 52 93 100 81 10 20 29 41 14 36 63 88 50 58 65 60
Packaging Pin-out and Package Information
4X
0.2 T L-M N
4X 25 TIPS 100 76
G 0.2 T L-M N C L
75
1
AB AB
X X = L, M, OR N
BV
3X VIEW
Y
AR
F B1 V1 J
51
25
26
A1 S1 A S
IN
4X
N
50
C
IM
2
4X
0.08 T
SEATING PLANE
100X
T
3
EL
0.05
VIEW AA
DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z 1 2 3
(W)
PR
1
2X
R R1
C2
0.25
GAGE PLANE
C1 (Z) VIEW AA
(K) E
CASE 983-02 ISSUE E
Figure 3-3 100-pin Thin Quad Flat Pack (TQFP) Mechanical Information
Preliminary Information 3-6 DSP56011 Technical Data Sheet, Rev. 1 MOTOROLA
Y
BASE METAL
L
M
VIEW Y
U
D
PLATING
0.08 M T L-M N
SECTION AB-AB
ROTATED 90 CLOCKWISE NOTES: 1. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M AND N TO BE DETERMINED AT THE SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B INCLUDE MOLD MISMATCH. 6. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.35. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07. MILLIMETERS MIN MAX 14.00 BSC 7.00 BSC 14.00 BSC 7.00 BSC --1.70 0.05 0.20 1.30 1.50 0.10 0.30 0.45 0.75 0.15 0.23 0.50 BSC 0.07 0.20 0.50 REF 0.08 0.20 16.00 BSC 8.00 BSC 0.09 0.16 16.00 BSC 8.00 BSC 0.20 REF 1.00 REF 0 7 0 -- 12 REF 12 REF
Packaging Ordering Drawings
ORDERING DRAWINGS
Complete mechanical information regarding DSP56011 packaging is available by facsimile through Motorola's MfaxTM system. Call the following number to obtain information by facsimile:
(602) 244-6609
The Mfax automated system requests the following information: * *
The receiving facsimile telephone number including area code or country code The caller's Personal Identification Number (PIN)
Note: For first time callers, the system provides instructions for setting up a PIN, which requires entry of a name and telephone number. * The type of information requested: - - - -
Instructions for using the system A literature order form
A total of three documents may be ordered per call. The DSP56011 100-pin TQFP package mechanical drawing is referenced as 983-02.
PR
Preliminary Information MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 3-7
EL
IM
Specific part technical information or data sheets Other information described by the system messages
IN
AR
Y
Packaging Ordering Drawings
PR
Preliminary Information 3-8 DSP56011 Technical Data Sheet, Rev. 1 MOTOROLA
EL
IM
IN
AR
Y
SECTION
4
DESIGN CONSIDERATIONS
THERMAL DESIGN CONSIDERATIONS
An estimation of the chip junction temperature, TJ, in C can be obtained from the equation: Equation 1: T J = T A + ( P D x R JA ) Where:
TA = ambient temperature C RJA = package junction-to-ambient thermal resistance C/W PD = power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: Equation 2: R JA = R JC + R CA
PR
MOTOROLA
EL
Where:
RJA = package junction-to-ambient thermal resistance C/W RJC = package junction-to-case thermal resistance C/W RCA = package case-to-ambient thermal resistance C/W RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or otherwise change the thermal dissipation capability of the area surrounding the device on a printed circuit board. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the printed circuit board, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool.
IM
DSP56011 Technical Data Sheet, Rev. 1
IN
Preliminary Information
AR
Y
4-1
Design Considerations Thermal Design Considerations
The thermal performance of plastic packages is more dependent on the temperature of the printed circuit board to which the package is mounted. Again, if the estimations obtained from RJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. A complicating factor is the existence of three common ways for determining the junction-to-case thermal resistance in plastic packages:
*
To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. If the temperature of the package case (TT) is determined by a thermocouple, the thermal resistance is computed using the value obtained by the equation (TJ - TT)/PD.
*
PR
Preliminary Information 4-2 DSP56011 Technical Data Sheet, Rev. 1 MOTOROLA
EL
As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual temperature. Hence, the new thermal metric, Thermal Characterization Parameter or JT, has been defined to be (TJ - TT)/PD. This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy.
IM
IN
AR
Y
*
To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink.
Design Considerations Electrical Design Considerations
ELECTRICAL DESIGN CONSIDERATIONS
CAUTION
This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC).
Use the following list of recommendations to assure correct DSP operation: * * * * * Provide a low-impedance path from the board power supply to each VCC pin on the DSP, and from the board ground to each GND pin. Use at least four 0.01-0.1 F bypass capacitors positioned as close as possible to the four sides of the package to connect the VCC power source to GND.
PR
* * *
MOTOROLA
EL
*
IM
Ensure that capacitor leads and associated printed circuit traces that connect to the chip VCC and GND pins are less than 0.5 in per capacitor lead.
Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VCC and GND.
Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This recommendation particularly applies to the address and data buses as well as the IRQA, IRQB, and NMI pins. Maximum Printed Circuit Board (PCB) trace lengths on the order of 6 inches are recommended. Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VCC and GND circuits.
All inputs must be terminated (i.e., not allowed to float) using CMOS levels, except as noted in Section 1. Take special care to minimize noise levels on the VCCP and GNDP pins. If multiple DSP56011 devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices.
DSP56011 Technical Data Sheet, Rev. 1
IN
Preliminary Information
AR
4-3
Y
Design Considerations Power Consumption Considerations
POWER CONSUMPTION CONSIDERATIONS
Power dissipation is a key issue in portable DSP applications. Some of the factors which affect current consumption are described in this section. Most of the current consumed by CMOS devices is Alternating Current (AC), which is charging and discharging the capacitances of the pins and internal nodes.
Equation 3: I = C x V x f where: C = node/pin capacitance V = voltage swing f = frequency of node/pin toggle
Example 4-1 Current Consumption
Equation 4:
I = 50 x 10
For applications that require very low current consumption:
PR
*
4-4
EL
* * * *
IM
Disable unused peripherals. Disable unused pin activity.
The Maximum Internal Current (ICCImax) value reflects the typical possible switching of the internal buses on best-case operation conditions, which is not necessarily a real application case. The Typical Internal Current (ICCItyp) value reflects the average switching of the internal buses on typical operating conditions.
Minimize the number of pins that are switching. Minimize the capacitive load on the pins. Connect the unused inputs to pull-up or pull-down resistors.
DSP56011 Technical Data Sheet, Rev. 1
IN
- 12
For an I/O pin loaded with 50 pF capacitance, operating at 5.5 V, and with a 81 MHz clock, toggling at its maximum possible rate (20 MHz), the current consumption is:
x 5.5 x 20 x 10 = 5.5mA
6
Preliminary Information MOTOROLA
AR
Y
Current consumption is described by the formula:
Design Considerations Power Consumption Considerations
Current consumption test code:
org p:RESET jmp org movep move move move move move nop rep move rep mov clr move rep mac move jmp nop jmp MAIN p:MAIN #$180000,x:$FFFD #0,r0 #0,r4 #0,r5 #$00FF,m0 #$00FF,m4 #256 r0,x:(r0)+ #256 r4,y:(r4)+ a l:(r0)+,a #30 x0,y0,a x:(r0)+,x0 a,p:(r5) TP1 MAIN
TP1
PR
Preliminary Information MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 4-5
EL
IM
IN
AR
y:(r4)+,y0
Y
Design Considerations Power-Up Considerations
POWER-UP CONSIDERATIONS
To power-up the device properly, ensure that the following conditions are met: * * * * Stable power is applied to the device according to the specifications in Table 2-3 (DC Electrical Characteristics). The external clock oscillator is active and stable. RESET is asserted according to the specifications in Table 2-7 (Reset, Stop, Mode Select, and Interrupt Timing).
At the beginning of the hardware reset procedure, the device might consume significantly more current than the specified typical supply current. This is because of contentions among the internal nodes being affected by the hardware reset signal until they reach their final hardware reset state.
PR
Preliminary Information 4-6 DSP56011 Technical Data Sheet, Rev. 1 MOTOROLA
EL
IM
IN
Care should be taken to ensure that the maximum ratings for all input voltages obey the restrictions on Table 2-1 (Maximum Ratings), at all phases of the power-up procedure. This may be achieved by powering the external clock, hardware reset, and mode selection circuits from the same power supply that is connected to the power supply pins of the chip.
AR
The following input pins are driven to valid voltage levels: DR, PINIT, MODA, MODB, and MODC.
Y
Design Considerations Host Port Considerations
HOST PORT CONSIDERATIONS
Careful synchronization is required when reading multi-bit registers that are written by another asynchronous system. This is a common problem when two asynchronous systems are connected. The situation exists in the Host Interface. The following paragraphs present considerations for proper operation.
Host Programming Considerations
*
Unsynchronized Reading of Receive Byte Registers--When reading receive byte registers, RXH or RXL, the host program should use interrupts or poll the RXDF flag which indicates that data is available. This assures that the data in the receive byte registers will be stable. Overwriting Transmit Byte Registers--The host program should not write to the transmit byte registers, TXH or TXL, unless the TXDE bit is set, indicating that the transmit byte registers are empty. This guarantees that the transmit byte registers will transfer valid data to the HRX register. Synchronization of Status Bits from DSP to Host--HC, HOREQ, DMA, HF3, HF2, TRDY, TXDE, and RXDF status bits are set or cleared from inside the DSP and read by the host processor (refer to the User's Manual for descriptions of these status bits). The host can read these status bits very quickly without regard to the clock rate used by the DSP, but the state of the bit could be changing during the read operation. Generally, this is not a system problem, since the bit will be read correctly in the next pass of any host polling routine. However, if the host asserts HEN for more than timing number 31, with a minimum cycle time of timing number 31 + 32, then these status bits are guaranteed to be stable. Exercise care when reading status bits HF3 and HF2 as an encoded pair. If the DSP changes HF3 and HF2 from 00 to 11, there is a small probability that the host could read the bits during the transition and receive 01 or 10 instead of 11. If the combination of HF3 and HF2 has significance, the host could read the wrong combination. Therefore, read the bits twice and check for consensus. Overwriting the Host Vector--The host program should change the Host Vector register only when the Host Command bit (HC) is clear. This change will guarantee that the DSP interrupt control logic will receive a stable vector. Cancelling a Pending Host Command Exception--The host processor may elect to clear the HC bit to cancel the host command exception request at any time before it is recognized by the DSP. Because the host does not know exactly when the exception will be recognized (due to exception processing synchronization and pipeline delays), the DSP may execute the host
*
*
PR
* *
MOTOROLA
EL
IM
DSP56011 Technical Data Sheet, Rev. 1
IN
Preliminary Information
AR
Y
4-7
Design Considerations Host Port Considerations
command exception after the HC bit is cleared. For these reasons, the HV bits must not be changed at the same time that the HC bit is cleared. * Variance in the Host Interface Timing--The Host Interface (HI) may vary (e.g. due to the PLL lock time at reset). Therefore, a host which attempts to load (bootstrap) the DSP should first make sure that the part has completed its HI port programming (e.g., by setting the INIT bit in ICR then polling it and waiting it to be cleared, then reading the ISR or by writing the TREQ/RREQ together with the INIT and then polling INIT, ISR, and the HOREQ pin).
*
Synchronization of Status Bits from Host to DSP--DMA, HF1, HF0, and HCP, HTDE, and HRDF status bits are set or cleared by the host processor side of the interface. These bits are individually synchronized to the DSP clock. (Refer to the User's Manual for descriptions of these status bits.) Reading HF0 and HF1 as an Encoded Pair--Care must be exercised when reading status bits HF0 and HF1 as an encoded pair, (i.e., the four combinations 00, 01, 10, and 11 each have significance). A very small probability exists that the DSP will read the status bits synchronized during transition. Therefore, HF0 and HF1 should be read twice and checked for consensus.
*
PR
Preliminary Information 4-8 DSP56011 Technical Data Sheet, Rev. 1 MOTOROLA
EL
IM
IN
AR
DSP Programming Considerations
Y
SECTION
5
ORDERING INFORMATION
Consult a Motorola Semiconductor sales office or authorized distributor to determine product availability and to place an order. Table 5-1 Ordering Information
Part Supply Voltage 5V 5V Package Type Pin Count
DSPA56011 DSPB56011
Note:
Thin Quad Flat Pack (TQFP)
The DSPA56011 and the DSPB56011 include factory-programmed ROM containing support for Dolby AC3 with DVD specifications. These parts can be used only be customers licensed for Dolby AC-3. Future products in the DSP56011 family will include other ROM-based options. For additional information on future part development, or to request customer-specific ROM-based support, call your local Motorola Semiconductor sales office or authorized distributor.
PR
Preliminary Information MOTOROLA DSP56011 Technical Data Sheet, Rev. 1 5-1
EL
IM
IN
Thin Quad Flat Pack (TQFP)
AR
100 100 95 95
Y
Frequency (MHz) Order Number XCA56011BU95 XCB56011BU95
OnCE, Mfax, and Symphony are trademarks of Motorola, Inc.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us: USA/Europe/Locations Not Listed: Motorola Literature Distribution P.O. Box 5405 Denver, Colorado 80217 303-675-2140 1 (800) 441-2447 Asia/Pacific: Motorola Semiconductors H.K. Ltd. 8B Tai Ping Industrial Park 51 Ting Kok Road Tai Po, N.T., Hong Kong 852-26629298 Technical Resource Center: 1 (800) 521-6274 DSP Helpline dsphelp@dsp.sps.mot.com Internet: http://www.motorola-dsp.com Japan: Nippon Motorola Ltd. SPD, Strategic Planning Office 4-32-1, Nishi-Gotanda Shinagawa-ku, Tokyo 141, Japan 81-3-5487-8488
MfaxTM: RMFAX0@email.sps.mot.com TOUCHTONE (602) 244-6609 US & Canada ONLY (800) 774-1848

▲Up To Search▲

Price & Availability of XCB56011BU95

	To Download XCB56011BU95 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .